Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples

2016-03-16 Thread Michael Neuling
> > > + psl_dsnctl |= (phb_index << (63-11)); > > > > > > Looking at the psl docs, cappunitid in the dsndctl is bits 6 to 13. > > So > > why 11 here? > > > Because on POWER8NVL, dsndctl bit 11 == phb_index == cappunitid. > Bits 6-10 and 12-13 do not change between POWER8 and

Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples

2016-03-16 Thread Philippe Bergheaud
Michael Neuling wrote: On Tue, 2016-03-15 at 15:26 +0100, Philippe Bergheaud wrote: Naples CPUs have two CAPI ports. Naples is an internal name, don't use that. Use POWER8NVL is the name we use in the kernel. alsi, it's a "chip" that has two CAPI ports, not the CPU. OK, I will

Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples

2016-03-15 Thread Michael Neuling
On Tue, 2016-03-15 at 15:26 +0100, Philippe Bergheaud wrote: > Naples CPUs have two CAPI ports. Naples is an internal name, don't use that. Use POWER8NVL is the name we use in the kernel. alsi, it's a "chip" that has two CAPI ports, not the CPU. > Configure the PSL to route data to > the

[PATCH] cxl: Configure the PSL for dual port CAPI on Naples

2016-03-15 Thread Philippe Bergheaud
Naples CPUs have two CAPI ports. Configure the PSL to route data to the port corresponding to the PHB index. Signed-off-by: Philippe Bergheaud --- drivers/misc/cxl/pci.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git