Frederic Barrat writes:
> The code change looks ok, but am I the only one to think the commit
> message doesn't match? The enable bit has always been in the PSL_CONTROL
> register, it was just badly documented on p8. What's been removed is
> much of the configuration found in PSL_TB_CTLSTAT.
>
Le 09/02/2018 à 05:10, Vaibhav Jain a écrit :
For PSL9 the time-base enable bit has moved from PSL_TB_CTLSTAT
register to PSL_CONTROL register. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for PSL9.
Hence this patch removes function write_timebase_ctrl_psl9() and its
On 09/02/18 15:10, Vaibhav Jain wrote:
For PSL9 the time-base enable bit has moved from PSL_TB_CTLSTAT
register to PSL_CONTROL register. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for PSL9.
Hence this patch removes function write_timebase_ctrl_psl9() and its
reference
Le 09/02/2018 à 05:10, Vaibhav Jain a écrit :
For PSL9 the time-base enable bit has moved from PSL_TB_CTLSTAT
register to PSL_CONTROL register. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for PSL9.
Hence this patch removes function write_timebase_ctrl_psl9() and its
re
For PSL9 the time-base enable bit has moved from PSL_TB_CTLSTAT
register to PSL_CONTROL register. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for PSL9.
Hence this patch removes function write_timebase_ctrl_psl9() and its
references from the code.
Signed-off-by: Vaibhav
