On Oct 14, 2011, at 2:52 AM, Kumar Gala wrote:
Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes issues for places we utilize PIR to index
into array like in debug
] powerpc/85xx: Setup secondary cores PIR with hard SMP id
Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes issues for places we utilize PIR to index
into array like
, 2011 1:23 PM
To: linuxppc-...@ozlabs.org
Subject: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id
Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, October 20, 2011 9:32 AM
To: Bhushan Bharat-R65777
Cc: linuxppc-...@ozlabs.org
Subject: Re: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard
SMP id
On Oct 19, 2011, at 10:53 PM
Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes issues for places we utilize PIR to index
into array like in debug exception handlers for finding the exception
stack.
Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes issues for places we utilize PIR to index
into array like in debug exception handlers for finding the exception
stack.
