Re: [PATCH -next] powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

2009-06-10 Thread Kumar Gala
On Jun 10, 2009, at 3:37 PM, Nate Case wrote: Some boot loaders may not enable L1 instruction/data cache. Check if data and instruction caches are enabled, and enable them if needed. Signed-off-by: Nate Case --- arch/powerpc/include/asm/reg_booke.h |2 + arch/powerpc/kernel/cpu_setup

[PATCH -next] powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

2009-06-10 Thread Nate Case
Some boot loaders may not enable L1 instruction/data cache. Check if data and instruction caches are enabled, and enable them if needed. Signed-off-by: Nate Case --- arch/powerpc/include/asm/reg_booke.h |2 + arch/powerpc/kernel/cpu_setup_fsl_booke.S | 49 +++-