Re: [v3 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-20 Thread Tony Breeds
On Wed, Jul 20, 2011 at 08:02:29AM -0500, Ayman Elkhashab wrote: > From: Ayman El-Khashab > > Adds a register to the config space for the 460sx. Changes the vc0 > detect to a pll detect. maps configuration space to test the link > status. changes the setup to enable gen2 devices to operate at

[v3 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-20 Thread Ayman Elkhashab
From: Ayman El-Khashab Adds a register to the config space for the 460sx. Changes the vc0 detect to a pll detect. maps configuration space to test the link status. changes the setup to enable gen2 devices to operate at gen2 speeds. fixes mapping that was not correct for the 460sx. added bit

Re: [v2 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-18 Thread Tony Breeds
On Mon, Jul 18, 2011 at 08:31:01AM -0500, Ayman El-Khashab wrote: > Yes, but I think that is correct for it to be "1". The data > sheets for these parts that I checked had bit 1 marked as > reserved. Only OMR1MSKL and OMR3MSKL had extra definitions > such as the _IO and _UOT. The parts I checke

Re: [v2 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-18 Thread Ayman El-Khashab
On Mon, Jul 18, 2011 at 02:01:15PM +1000, Tony Breeds wrote: > On Fri, Jul 15, 2011 at 11:40:27AM -0500, Ayman Elkhashab wrote: > > > @@ -1582,8 +1628,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct > > ppc4xx_pciex_port *port, > > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, la

Re: [v2 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-17 Thread Tony Breeds
On Fri, Jul 15, 2011 at 11:40:27AM -0500, Ayman Elkhashab wrote: > @@ -1582,8 +1628,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct > ppc4xx_pciex_port *port, > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);

[v2 PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-15 Thread Ayman Elkhashab
From: Ayman El-Khashab Adds a register to the config space for the 460sx. Changes the vc0 detect to a pll detect. maps configuration space to test the link status. changes the setup to enable gen2 devices to operate at gen2 speeds. fixes mapping that was not correct for the 460sx. added bit

Re: [PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-14 Thread Benjamin Herrenschmidt
On Thu, 2011-07-14 at 11:04 -0500, Ayman El-Khashab wrote: > Thanks Tony, some comments below. > > On Thu, Jul 14, 2011 at 11:16:27AM +1000, Tony Breeds wrote: > > > > > +static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port > > > *port) > > > +{ > > > + void __iomem *mbase; > >

Re: [PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-14 Thread Ayman El-Khashab
Thanks Tony, some comments below. On Thu, Jul 14, 2011 at 11:16:27AM +1000, Tony Breeds wrote: > > > +static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port > > *port) > > +{ > > + void __iomem *mbase; > > + int attempt = 50; > > + > > + port->link = 0; > > + > > + mbase

Re: [PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-13 Thread Tony Breeds
On Wed, Jul 13, 2011 at 07:33:31PM -0500, Ayman El-Khashab wrote: > Adds a register to the config space for the 460sx. Changes the vc0 > detect to a pll detect. maps configuration space to test the link > status. changes the setup to enable gen2 devices to operate at gen2 > speeds. fixes mappin

[PATCH 1/1] powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

2011-07-13 Thread Ayman El-Khashab
Adds a register to the config space for the 460sx. Changes the vc0 detect to a pll detect. maps configuration space to test the link status. changes the setup to enable gen2 devices to operate at gen2 speeds. fixes mapping that was not correct for the 460sx. tested on the 460sx eiger and custo