Re: [PATCH 1/2] powerpc: sstep: Fix load and update instructions

On 11/19/20 11:11 AM, Sandipan Das wrote: The Power ISA says that the fixed-point load and update instructions must neither use R0 for the base address (RA) nor have the destination (RT) and the base address (RA) as the same register. In these cases, the instruction is invalid. This applies to

Re: [PATCH 1/2] powerpc: sstep: Fix load and update instructions

Hi, On 25/11/20 3:39 pm, Ravi Bangoria wrote: > >> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c >> index 855457ed09b5..25a5436be6c6 100644 >> --- a/arch/powerpc/lib/sstep.c >> +++ b/arch/powerpc/lib/sstep.c >> @@ -2157,11 +2157,15 @@ int analyse_instr(struct instruction_op *op

Re: [PATCH 1/2] powerpc: sstep: Fix load and update instructions

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 855457ed09b5..25a5436be6c6 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -2157,11 +2157,15 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 23: /* lwzx */

[PATCH 1/2] powerpc: sstep: Fix load and update instructions

The Power ISA says that the fixed-point load and update instructions must neither use R0 for the base address (RA) nor have the destination (RT) and the base address (RA) as the same register. In these cases, the instruction is invalid. This applies to the following instructions. * Load Byte and