From: Simon Guo
The transaction memory checkpoint area save/restore behavior is
triggered when VCPU qemu process is switching out/into CPU. ie.
at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr().
MSR TM active state is determined by TS bits:
active: 10(transactional) or 01 (suspende
On Thu, Jan 11, 2018 at 06:11:29PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> The transaction memory checkpoint area save/restore behavior is
> triggered when VCPU qemu process is switching out/into CPU. ie.
> at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr().
>
> MSR
Hi Paul,
On Tue, Jan 23, 2018 at 05:04:09PM +1100, Paul Mackerras wrote:
> On Thu, Jan 11, 2018 at 06:11:29PM +0800, wei.guo.si...@gmail.com wrote:
> > From: Simon Guo
> >
> > The transaction memory checkpoint area save/restore behavior is
> > triggered when VCPU qemu process is switching out/int