Valentine Barshak wrote:
David Gibson wrote:
On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels (two transmit and two receive).
Each channel is dedicated to one of two EMAC cores.
This patch fixes
On Thu, 20 Sep 2007 22:46:18 +0400
Valentine Barshak [EMAIL PROTECTED] wrote:
Valentine Barshak wrote:
David Gibson wrote:
On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels (two transmit and
Josh Boyer wrote:
On Thu, 20 Sep 2007 22:46:18 +0400
Valentine Barshak [EMAIL PROTECTED] wrote:
Valentine Barshak wrote:
David Gibson wrote:
On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels
David Gibson wrote:
On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels (two transmit and two receive).
Each channel is dedicated to one of two EMAC cores.
This patch fixes Sequoia DTS MAL0 entry and
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels (two transmit and two receive).
Each channel is dedicated to one of two EMAC cores.
This patch fixes Sequoia DTS MAL0 entry and EMAC entries,
assigning correct channel numbers to EMACs.
Signed-off-by: Valentine Barshak
On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
According to PowerPC 440EPx documentation,
MAL0 is comprised of four channels (two transmit and two receive).
Each channel is dedicated to one of two EMAC cores.
This patch fixes Sequoia DTS MAL0 entry and EMAC entries,
