On Mar 14, 2012, at 5:15 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>
> The bootloader sets the PCI bridge to open a window from 0x
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> res
From: chenhui zhao
There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
southbridge chip.
The bootloader sets the PCI bridge to open a window from 0x
to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
resource. In the routine pci_read_bridge_io(), if the base which
is re
