Re: [PATCH 4/4] powerpc/smp: Add Power9 scheduler topology

2017-08-31 Thread Srikar Dronamraju
> +static struct sched_domain_topology_level power9_topology[] = { > +#ifdef CONFIG_SCHED_SMT > + { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, > +#endif > + { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, > + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, > +

Re: [PATCH 4/4] powerpc/smp: Add Power9 scheduler topology

2017-08-31 Thread Michael Ellerman
Oliver O'Halloran writes: > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > index 46f071cedf31..7b2ed0d6fc96 100644 > --- a/arch/powerpc/kernel/smp.c > +++ b/arch/powerpc/kernel/smp.c > @@ -1043,7 +1081,19 @@ void __init smp_cpus_done(unsigned int max_cpus)

[PATCH 4/4] powerpc/smp: Add Power9 scheduler topology

2017-06-29 Thread Oliver O'Halloran
In previous generations of Power processors each core had a private L2 cache. The Power 9 processor has a slightly different design where the L2 cache is shared among pairs of cores rather than being completely private. Making the scheduler aware of this cache sharing allows the scheduler to make