On 06/02/2014 07:45 PM, Scott Wood wrote:
On Mon, 2014-06-02 at 15:48 +0300, Tudor Laurentiu wrote:
On 05/31/2014 01:45 AM, Scott Wood wrote:
From: Laurentiu Tudor laurentiu.tu...@freescale.com
- resent since the original didn't make it to the list archives
or patchwork.
The only
On 05/31/2014 01:45 AM, Scott Wood wrote:
From: Laurentiu Tudor laurentiu.tu...@freescale.com
Virtualized environments may expose a e6500 dual-threaded core
as two single-threaded e6500 cores. Take advantage of this
and get rid of the tlb lock and the trap-causing tlbsx in
the htw miss handler
On Mon, 2014-06-02 at 15:48 +0300, Tudor Laurentiu wrote:
On 05/31/2014 01:45 AM, Scott Wood wrote:
From: Laurentiu Tudor laurentiu.tu...@freescale.com
- resent since the original didn't make it to the list archives
or patchwork.
The only thing i can think of is that maybe i've
From: Laurentiu Tudor laurentiu.tu...@freescale.com
Virtualized environments may expose a e6500 dual-threaded core
as two single-threaded e6500 cores. Take advantage of this
and get rid of the tlb lock and the trap-causing tlbsx in
the htw miss handler by guarding with CPU_FTR_SMT, as it's
