On Tue, Jul 29, 2014 at 10:46:13AM +0100, Mark Rutland wrote:
> > + - big-endian : If this property is absent, the native endian mode will
> > + be in use as default, or the big endian mode will be in
> > use
> > + for all the device registers.
>
> Native endian
> + - big-endian : If this property is absent, the native endian mode will
> + be in use as default, or the big endian mode will be in use
> + for all the device registers.
Native endian is meaningless. If a CPU supports both BE and LE, there is
no native endianne
On Fri, Jul 25, 2014 at 11:47:42AM +0530, Varka Bhadram wrote:
> Hi Nicolin,
>
> On 07/25/2014 11:24 AM, Nicolin Chen wrote:
> >Hi Varka,
> >
> >Regarding a point you suggested.
> >
> >On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
> >>On 07/25/2014 09:33 AM, Nicolin Chen wrote
Hi Nicolin,
On 07/25/2014 11:24 AM, Nicolin Chen wrote:
Hi Varka,
Regarding a point you suggested.
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
On 07/25/2014 09:33 AM, Nicolin Chen wrote:
(...)
+
+static const struct platform_device_id fsl_asrc_devtype[] = {
+ {
Hi Varka,
Regarding a point you suggested.
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
> On 07/25/2014 09:33 AM, Nicolin Chen wrote:
> (...)
>
> >+
> >+static const struct platform_device_id fsl_asrc_devtype[] = {
> >+{
> >+.name = "imx35-asrc",
> >+
Hi Varka,
On Fri, Jul 25, 2014 at 09:54:43AM +0530, Varka Bhadram wrote:
> On 07/25/2014 09:33 AM, Nicolin Chen wrote:
> >The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
> >signal associated with an input clock into a signal associated with a
> >different
> >output c
On 07/25/2014 09:33 AM, Nicolin Chen wrote:
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links such as ESAI<->CS42888 and SSI<->WM8962 and SA
