pci_update_resource() might be called to update (shift) IOV BARs in PPC PowerNV specific pcibios_sriov_enable() when enabling PF's SRIOV capability. At that point, the PF have been functional if the SRIOV is enabled through sysfs entry "sriov_numvfs". The PF's memory decoding (0x2 in PCI_COMMAND) shouldn't be disabled when updating its IOV BARs with pci_update_resource(). Otherwise, we receives EEH error caused by MMIO access to PF's memory BARs during the window when PF's memory decoding is disabled.
sriov_numvfs_store pdev->driver->sriov_configure mlx5_core_sriov_configure pci_enable_sriov sriov_enable pcibios_sriov_enable pnv_pci_sriov_enable pnv_pci_vf_resource_shift pci_update_resource This disables VF's memory space instead of PF's memory decoding when 64-bits IOV BARs are updated in pci_update_resource(). Reported-by: Carol Soto <cls...@us.ibm.com> Suggested-by: Bjorn Helgaas <bhelg...@google.com> Signed-off-by: Gavin Shan <gws...@linux.vnet.ibm.com> Tested-by: Carol Soto <cls...@us.ibm.com> --- drivers/pci/setup-res.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 66c4d8f..1456896 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -29,10 +29,10 @@ void pci_update_resource(struct pci_dev *dev, int resno) { struct pci_bus_region region; - bool disable; - u16 cmd; + bool disable = false; + u16 cmd, bit; u32 new, check, mask; - int reg; + int reg, cmd_reg; enum pci_bar_type type; struct resource *res = dev->resource + resno; @@ -81,11 +81,23 @@ void pci_update_resource(struct pci_dev *dev, int resno) * disable decoding so that a half-updated BAR won't conflict * with another device. */ - disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; + if (res->flags & IORESOURCE_MEM_64) { + if (resno <= PCI_ROM_RESOURCE) { + disable = !dev->mmio_always_on; + cmd_reg = PCI_COMMAND; + bit = PCI_COMMAND_MEMORY; + } else { +#ifdef CONFIG_PCI_IOV + disable = true; + cmd_reg = dev->sriov->pos + PCI_SRIOV_CTRL; + bit = PCI_SRIOV_CTRL_MSE; +#endif + } + } + if (disable) { - pci_read_config_word(dev, PCI_COMMAND, &cmd); - pci_write_config_word(dev, PCI_COMMAND, - cmd & ~PCI_COMMAND_MEMORY); + pci_read_config_word(dev, cmd_reg, &cmd); + pci_write_config_word(dev, cmd_reg, cmd & ~bit); } pci_write_config_dword(dev, reg, new); @@ -107,7 +119,7 @@ void pci_update_resource(struct pci_dev *dev, int resno) } if (disable) - pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_write_config_word(dev, cmd_reg, cmd); } int pci_claim_resource(struct pci_dev *dev, int resource) -- 2.1.0