On Mar 13, 2009, at 5:06 PM, Kumar Gala wrote:
On Mar 13, 2009, at 4:26 PM, Benjamin Herrenschmidt wrote:
+BEGIN_FTR_SECTION
+ b TlbWo/* Code for TLB-errata workaround doesn't fit
here */
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
+RFTlbWo:
Can you use nicer label names ?
On Mar 13, 2009, at 4:26 PM, Benjamin Herrenschmidt wrote:
+BEGIN_FTR_SECTION
+ b TlbWo/* Code for TLB-errata workaround doesn't fit
here */
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
+RFTlbWo:
Can you use nicer label names ? :-)
Also, that's a lot of code for such a hot pa
> +BEGIN_FTR_SECTION
> + b TlbWo/* Code for TLB-errata workaround doesn't fit here */
> +END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
> +RFTlbWo:
Can you use nicer label names ? :-)
Also, that's a lot of code for such a hot path...
Cheers,
Ben.
_
On Fri, 2009-03-13 at 10:16 -0500, Kumar Gala wrote:
> From: David Jander
>
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workaround in
> fo
From: David Jander
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Signed-off-by: David Ja