On Wed, 2008-06-18 at 13:38 -0600, John Rigby wrote:
> Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
> problem is an internal bridge that the processor can not snoop across.
I do not have access to the manuals right now but I search all over an
this was not something I fou
Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
problem is an internal bridge that the processor can not snoop across.
On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <[EMAIL PROTECTED]> wrote:
> I have tried to speed up u-boot by turning on I/D cache during boot.
>
> It
