[v2 PATCH 2/2] powerpc: Enable CPU_FTR_ASYM_SMT for interleaved big-cores

2018-07-03 Thread Gautham R. Shenoy
From: "Gautham R. Shenoy" A pair of IBM POWER9 SMT4 cores can be fused together to form a big-core with 8 SMT threads. This can be discovered via the "ibm,thread-groups" CPU property in the device tree which will indicate which group of threads that share the L1 cache, translation cache and instr

Re: [v2 PATCH 2/2] powerpc: Enable CPU_FTR_ASYM_SMT for interleaved big-cores

2018-07-03 Thread Murilo Opsfelder Araujo
On Tue, Jul 03, 2018 at 04:33:51PM +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > A pair of IBM POWER9 SMT4 cores can be fused together to form a big-core > with 8 SMT threads. This can be discovered via the "ibm,thread-groups" > CPU property in the device tree which will indicat

Re: [v2 PATCH 2/2] powerpc: Enable CPU_FTR_ASYM_SMT for interleaved big-cores

2018-07-04 Thread Gautham R Shenoy
Hi Murilo, Thanks for the review. On Tue, Jul 03, 2018 at 02:53:46PM -0300, Murilo Opsfelder Araujo wrote: [..snip..] > > -/* Initialize CPU <=> thread mapping/ > > + if (has_interleaved_big_core) { > > + int key = __builtin_ctzl(CPU_FTR_ASYM_SMT); > > + > > + cur_c

Re: [v2 PATCH 2/2] powerpc: Enable CPU_FTR_ASYM_SMT for interleaved big-cores

2018-07-04 Thread Murilo Opsfelder Araujo
On Wed, Jul 04, 2018 at 01:45:05PM +0530, Gautham R Shenoy wrote: > Hi Murilo, > > Thanks for the review. > > On Tue, Jul 03, 2018 at 02:53:46PM -0300, Murilo Opsfelder Araujo wrote: > [..snip..] > > > > -/* Initialize CPU <=> thread mapping/ > > > + if (has_interleaved_big_core) { > > >