bject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
>
> On 07/30/2013 11:22:54 AM, Bhushan Bharat-R65777 wrote:
> > diff --git a/arch/powerpc/kvm/e500_mmu_host.c
> > b/arch/powerpc/kvm/e500_mmu_host.c
> > index 5cbdc8f..a48c13f 100644
> > --
On 07/30/2013 11:22:54 AM, Bhushan Bharat-R65777 wrote:
diff --git a/arch/powerpc/kvm/e500_mmu_host.c
b/arch/powerpc/kvm/e500_mmu_host.c
index 5cbdc8f..a48c13f 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -40,6 +40,84 @@
static struct kvmppc_e500_tlb
t-B07421
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
>
> On Fri, 2013-07-26 at 15:03 +, Bhushan Bharat-R65777 wrote:
> > Will not searching the Linux PTE is a overkill?
>
> That's the best approach. Also we are searching it already to
On Fri, 2013-07-26 at 15:03 +, Bhushan Bharat-R65777 wrote:
> Will not searching the Linux PTE is a overkill?
That's the best approach. Also we are searching it already to resolve
the page fault. That does mean we search twice but on the other hand
that also means it's hot in the cache.
Cheer
rg;
> linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Bhushan Bharat-R65777
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
>
>
> On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
>
> > On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhush
rg;
> linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Bhushan Bharat-R65777
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
>
>
> On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
>
> > On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhush
Scott-B07421; Bhushan Bharat-R65777
> Subject: Re: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages
>
> On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> > If the page is RAM then map this as cacheable and coherent (set "M"
> > bit) otherwi
On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
> On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
>> If the page is RAM then map this as cacheable and coherent (set "M" bit)
>> otherwise this page is treated as I/O and map this as cache inhibited
>> and guarded (set "I + G")
>>
On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> If the page is RAM then map this as cacheable and coherent (set "M" bit)
> otherwise this page is treated as I/O and map this as cache inhibited
> and guarded (set "I + G")
>
> This helps setting proper MMU mapping for direct assigned dev
