From: Scott Wood [mailto:scottw...@freescale.com]
On Thu, 2014-03-20 at 11:59 +, David Laight wrote:
I tried to work out what the 'twi, isync' instructions were for (in
in_le32()).
The best I could come up with was to ensure a synchronous bus-fault.
But bus faults are probably only
On Fri, 2014-03-21 at 09:21 +, David Laight wrote:
From: Scott Wood [mailto:scottw...@freescale.com]
On Thu, 2014-03-20 at 11:59 +, David Laight wrote:
I tried to work out what the 'twi, isync' instructions were for (in
in_le32()).
The best I could come up with was to ensure a
On Tue, Mar 18, 2014 at 06:18:54PM -0500, Scott Wood wrote:
The sequence write, readback, sync will guarantee this according to the
manual.
If you're referring to the section you quoted above, the manual does not
say that. It only talks about when accesses to memory regions affected
From: Kevin Hao
Sent: 20 March 2014 11:48
To: Scott Wood
Cc: linuxppc-dev@lists.ozlabs.org; Chenhui Zhao; jason@freescale.com;
linux-ker...@vger.kernel.org
Subject: Re: [PATCH 9/9] powerpc/pm: support deep sleep feature on T1040
On Tue, Mar 18, 2014 at 06:18:54PM -0500, Scott Wood
On Thu, 2014-03-20 at 11:59 +, David Laight wrote:
I tried to work out what the 'twi, isync' instructions were for (in
in_le32()).
The best I could come up with was to ensure a synchronous bus-fault.
But bus faults are probably only expected during device probing - not
normal operation,
On Thu, 2014-03-20 at 19:47 +0800, Kevin Hao wrote:
OK, so the intention of 'twi, isync' following the load is not to order the
following storage access, but order the following delay loop instructions,
right? But according to the e6500 manual, the instructions complete in order.
The following
On Wed, 2014-03-19 at 08:56 +0800, Chenhui Zhao wrote:
On Tue, Mar 18, 2014 at 05:42:09PM -0500, Scott Wood wrote:
On Mon, 2014-03-17 at 19:19 +0800, Chenhui Zhao wrote:
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
Why do you need the entry mapping on 32-bit but not
On Mon, 2014-03-17 at 19:19 +0800, Chenhui Zhao wrote:
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
On Sun, 2014-03-16 at 12:58 +0800, Kevin Hao wrote:
On Fri, Mar 14, 2014 at 05:26:27PM -0500, Scott Wood wrote:
On Thu, 2014-03-13 at 15:46 +0800, Kevin Hao wrote:
On Wed, Mar 12, 2014 at 12:43:05PM -0500, Scott Wood wrote:
Shouldn't we use readback, sync here? The following is quoted
On Tue, Mar 18, 2014 at 05:42:09PM -0500, Scott Wood wrote:
On Mon, 2014-03-17 at 19:19 +0800, Chenhui Zhao wrote:
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
On Fri, Mar 14, 2014 at 05:26:27PM -0500, Scott Wood wrote:
On Thu, 2014-03-13 at 15:46 +0800, Kevin Hao wrote:
On Wed, Mar 12, 2014 at 12:43:05PM -0500, Scott Wood wrote:
Shouldn't we use readback, sync here? The following is quoted form
t4240RM:
To guarantee that the results of
On Thu, 2014-03-13 at 15:46 +0800, Kevin Hao wrote:
On Wed, Mar 12, 2014 at 12:43:05PM -0500, Scott Wood wrote:
Shouldn't we use readback, sync here? The following is quoted form
t4240RM:
To guarantee that the results of any sequence of writes to configuration
registers are in
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
On Wed, Mar 12, 2014 at 12:43:05PM -0500, Scott Wood wrote:
Shouldn't we use readback, sync here? The following is quoted form
t4240RM:
To guarantee that the results of any sequence of writes to configuration
registers are in effect, the final configuration register write should be
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it
On Wed, 2014-03-12 at 13:57 +0800, Kevin Hao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
+ FSL_DIS_ALL_IRQ
+
+ /*
+ * Place DDR controller in self refresh mode.
+ * From here on, DDR can't be access any more.
+ */
+ lwz r10, 0(r13)
+ oris
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it becomes more
energy-efficient.
The DDR controller will also be
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
+ FSL_DIS_ALL_IRQ
+
+ /*
+* Place DDR controller in self refresh mode.
+* From here on, DDR can't be access any more.
+*/
+ lwz r10, 0(r13)
+ orisr10, r10, CCSR_DDR_SDRAM_CFG_2_FRC_SR@h
+
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