Hi Ben,
On 08.11.2007, 2:19:33 you wrote: > On Thu, 2007-11-08 at 02:12 +0300, Yuri Tikhonov wrote: >> This is the updated patch for support synchronization of L2-Cache with >> the external memory on the ppc44x-based platforms. >> >> Differencies against the previous patch-set: >> - remove L2_CACHE config option; >> - introduce the ppc machdep to invalidate L2 cache lines; >> - some code clean-up. > Can you tell me more about how this cache operates ? I don't quite > understand why you would invalidate it on bidirectional DMAs rather than > flush it to memory (unless you get your terminology wrong) and why you > wouldn't flush it on transfers to the device.. Unless it is a > write-through cache ? Yes, the ppc44x Level2 cache has the write-through design, so no need to do any kind of l2_flush. As far as the DMA_BIDIRECTIONAL case is concerned flush_dcache_range() flushes the data over the following path: L1->L2->RAM, but invalidates L1 only, and L2 remains invalid. Since in the BIDIRECTIONAL case DMA may update the data in RAM - we have to invalidate L2-cache manually, so that CPU may read new data transmitted by DMA right from RAM rather than old ones stuck in L2 due to flush_dcache(). Regards, Yuri -- Yuri Tikhonov, Senior Software Engineer Emcraft Systems, www.emcraft.com _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev