On 4/1/20 11:59 AM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be able to dynamically find actual number of watchpoi
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
With Book3s DAWR, ptrace and perf watchpoints on powerpc behaves
differently. Ptrace watchpoint works in one-shot mode and generates
signal before executing instruction. It's ptrace user's job to
single-step the instruction and re-enable the watch
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to set_dawr() which indicates which DAWR
should be programed.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 4 ++--
arch/powerpc/kernel/dawr.c | 15 ++-
ar
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/debug.h | 2 +-
arch/powerpc/
Le 01/04/2020 à 08:50, Ravi Bangoria a écrit :
On 4/1/20 11:59 AM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be
Subscribe to the MCE notification and add the physical address which
generated a memory error to nvdimm bad range.
Signed-off-by: Santosh Sivaraj
---
This patch depends on "powerpc/mce: Add MCE notification chain" [1].
Unlike the previous series[2], the patch adds badblock registration only for
Hi,
On Wed, Apr 01, 2020 at 01:42:27PM +0800, Baoquan He wrote:
> On 04/01/20 at 12:56am, Mike Rapoport wrote:
> > On Mon, Mar 30, 2020 at 11:58:43AM +0200, Michal Hocko wrote:
> > >
> > > What would it take to make ia64 use HAVE_MEMBLOCK_NODE_MAP? I would
> > > really love to see that thing go a
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This series adds support for OpenCAPI Persistent Memory devices on bare metal
> (arch/powernv), exposing them as nvdimms so that we can make use of the
> existing infrastructure. There already exists a driver for the same devices
> ab
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Add OPAL calls for LPC memory alloc/release
>
This seems to be referencing an existing api definition, can you
include a pointer to the spec in case someone wanted to understand
what these routines do? I suspect this is not allocating m
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> When setting up OpenCAPI connected persistent memory, the range check may
> not be performed until quite late (or perhaps not at all, if the user does
> not establish a DAX device).
>
> This patch makes the range check callable so we can
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch adds OPAL calls to powernv so that the OpenCAPI
> driver can map & release LPC (Lowest Point of Coherency) memory.
>
> Signed-off-by: Alastair D'Silva
> Reviewed-by: Andrew Donnellan
> ---
> arch/powerpc/include/asm/pnv-oc
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Function declarations don't need externs, remove the existing ones
> so they are consistent with newer code
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Andrew Donnellan
> Acked-by: Frederic Barrat
Looks good.
> ---
> arch/powe
On Sun, Mar 29, 2020 at 10:53 PM Alastair D'Silva wrote:
>
> OpenCAPI LPC memory is allocated per link, but each link supports
> multiple AFUs, and each AFU can have LPC memory assigned to it.
Is there an OpenCAPI primer to decode these objects and their
associations that I can reference?
>
> T
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch addresses warnings and errors from the kernel doc scripts for
> the OpenCAPI driver.
>
> It also makes minor tweaks to make the docs more consistent.
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Andrew Donnellan
> ---
>
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Add functions to map/unmap LPC memory
>
"map memory" is an overloaded term. I'm guessing this patch has
nothing to do with mapping memory in the MMU. Is it updating hardware
resource decoders to start claiming address space that was all
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch emits a message showing how much LPC memory & special purpose
> memory was detected on an OCXL device.
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Frederic Barrat
> Acked-by: Andrew Donnellan
> ---
> drivers/misc/ocxl/
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This driver exposes LPC memory on OpenCAPI pmem cards
> as an NVDIMM, allowing the existing nvram infrastructure
> to be used.
>
> Namespace metadata is stored on the media itself, so
> scm_reserve_metadata() maps 1 section's worth of PM
Add new module driver for new ASRC in i.MX8MN, several commits
are added for new property fsl,asrc-format
Shengjiu Wang (7):
ASoC: fsl_asrc: rename asrc_priv to asrc
ASoC: dt-bindings: fsl_asrc: Add new property fsl,asrc-format
ASoC: fsl-asoc-card: Support new property fsl,asrc-format
ASoC
In order to move common structure to fsl_asrc_common.h
we change the name of asrc_priv to asrc, the asrc_priv
will be used by new struct fsl_asrc_priv.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 298 +--
sound/soc/fsl/fsl_asrc.h | 4 +-
In order to support new EASRC and simplify the code structure,
We decide to share the common structure between them. This bring
a problem that EASRC accept format directly from devicetree, but
ASRC accept width from devicetree.
In order to align with new ESARC, we add new property fsl,asrc-format.
In order to align with new ESARC, we add new property fsl,asrc-format.
The fsl,asrc-format can replace the fsl,asrc-width, driver
can accept format from devicetree, don't need to convert it to
format through width.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl-asoc-card.c | 21 -
In order to align with new ESARC, we add new property fsl,asrc-format.
The fsl,asrc-format can replace the fsl,asrc-width, driver
can accept format from devicetree, don't need to convert it to
format through width.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 40 ++
There is a new ASRC included in i.MX serial platform, there
are some common definition can be shared with each other.
So move the common definition to a separate header file.
And add fsl_asrc_pair_priv and fsl_asrc_priv for
the variable specific for the module, which can be used
internally.
Signe
EASRC (Enhanced Asynchronous Sample Rate Converter) is a new
IP module found on i.MX8MN.
Signed-off-by: Shengjiu Wang
---
.../devicetree/bindings/sound/fsl,easrc.yaml | 101 ++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,easr
EASRC (Enhanced Asynchronous Sample Rate Converter) is a new IP module
found on i.MX8MN. It is different with old ASRC module.
The primary features for the EASRC are as follows:
- 4 Contexts - groups of channels with an independent time base
- Fully independent and concurrent context control
- Sim
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/incl
On 4/1/20 12:03 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only first watchpoint, disable all available
watchpoints while clearing dawr_force_enable.
Can you also explain why you change the function name ?
Right. I should have. Will a
On Wed, Apr 01, 2020 at 04:45:34PM +0800, Shengjiu Wang wrote:
> In order to move common structure to fsl_asrc_common.h
> we change the name of asrc_priv to asrc, the asrc_priv
> will be used by new struct fsl_asrc_priv.
>
> Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
static void set_debug_reg_defaults(struct thread_struct *thread)
{
- thread->hw_brk.address = 0;
- thread->hw_brk.type = 0;
- thread->hw_brk.len = 0;
- thread->hw_brk.hw_len = 0;
- if (ppc_breakpoint_available())
- set_breakpoint(&thread->hw_brk);
+ int i;
+
+ fo
> On 20-Mar-2020, at 1:27 AM, Jarkko Sakkinen
> wrote:
>
> On Wed, Mar 18, 2020 at 09:00:17PM -0400, Stefan Berger wrote:
>> From: Stefan Berger
>>
>> This patch fixes the following problem when the ibmvtpm driver
>> is built as a module:
>>
>> ERROR: modpost: "tpm2_get_cc_attrs_tbl" [driv
Le 01/04/2020 à 10:57, Ravi Bangoria a écrit :
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Sig
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make supporting more watchpoints very easy.
With more than o
On 4/1/20 12:02 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only one watchpoint, get num of available
watchpoints dynamically and disable all of them.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 15 +
Le 01/04/2020 à 11:13, Ravi Bangoria a écrit :
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make suppor
On 4/1/20 2:50 PM, Christophe Leroy wrote:
Le 01/04/2020 à 11:13, Ravi Bangoria a écrit :
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use
On Tue, Mar 31, 2020 at 09:00:21PM -0300, Leonardo Bras wrote:
> During a crash, there is chance that the cpus that handle the NMI IPI
> are holding a spin_lock. If this spin_lock is needed by crashing_cpu it
> will cause a deadlock. (rtas.lock and printk logbuf_lock as of today)
>
> This is a pro
Hi Gautham,
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Currently when CPU goes idle, we take a snapshot of PURR via
pseries_idle_prolog() which is used at the CPU idle exit to compute
the idle PURR cycles via the function pseries_idle_epilog(). Thus,
the value of idle PURR cycle thus
Le 01/04/2020 à 11:11, Christophe Leroy a écrit :
Le 01/04/2020 à 10:57, Ravi Bangoria a écrit :
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Add documentation for the following sysfs interfaces:
/sys/devices/system/cpu/cpuX/purr
/sys/devices/system/cpu/cpuX/spurr
/sys/devices/system/cpu/cpuX/idle_purr
/sys/devices/system/cpu/cpuX/idle_spurr
Signed-off-by: Gautham R. Shenoy
---
Do
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Currently purr, spurr, idle_purr, idle_spurr are exposed for every CPU
via the sysfs interface
/sys/devices/system/cpu/cpuX/[idle_][s]purr. Each sysfs read currently
generates an IPI to obtain the desired value from the target CPU X.
Since thes
When we enter into fadump crash path via system reset we fail to update
the pstore.
On the system reset path we first update the pstore then we go for fadump
crash. But the problem here is when all the CPUs try to get the pstore
lock to initiate the pstore write, only one CPUs will acquire the loc
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
Michal Simek writes:
> On 01. 04. 20 4:07, Michael Ellerman wrote:
>> Michal Simek writes:
>>> Hi,
>>>
>>> recently we wanted to update xilinx intc driver and we found that function
>>> which we wanted to remove is still wired by ancient Xilinx PowerPC
>>> platforms. Here is the thread about it.
On Wed, 01 Apr 2020 12:35:16 +0200,
Michael Ellerman wrote:
>
> Michal Simek writes:
> > On 01. 04. 20 4:07, Michael Ellerman wrote:
> >> Michal Simek writes:
> >>> Hi,
> >>>
> >>> recently we wanted to update xilinx intc driver and we found that function
> >>> which we wanted to remove is still
Balamuruhan S wrote:
add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
* with same dividend and divisor to have undefine RT
for divdeu[.]
* with divide by zero to have undefine RT for both
divde[.] and divdeu[.]
On Wed, 2020-04-01 at 16:26 +0530, Naveen N. Rao wrote:
> Balamuruhan S wrote:
> > add testcases for divde, divde., divdeu, divdeu. emulated
> > instructions to cover few scenarios,
> > * with same dividend and divisor to have undefine RT
> > for divdeu[.]
> > * with divid
On 01. 04. 20 12:38, Takashi Iwai wrote:
> On Wed, 01 Apr 2020 12:35:16 +0200,
> Michael Ellerman wrote:
>>
>> Michal Simek writes:
>>> On 01. 04. 20 4:07, Michael Ellerman wrote:
Michal Simek writes:
> Hi,
>
> recently we wanted to update xilinx intc driver and we found that fun
Le 31/03/2020 à 17:22, Christophe Leroy a écrit :
That's first try to port PPC64 syscall entry/exit logic in C to PPC32.
I've do the minimum to get it work. I have not reworked calls
to sys_fork() and friends for instance.
For the time being, it seems to work more or less but:
- ping reports
Hello Naveen,
On Wed, Apr 01, 2020 at 03:28:48PM +0530, Naveen N. Rao wrote:
> Gautham R. Shenoy wrote:
> >From: "Gautham R. Shenoy"
> >
[..snip..]
> >-static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
> >-static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
> > static DEVICE_ATTR(pir, 0400
On Mon, 2019-08-12 at 21:50:43 UTC, Nick Desaulniers wrote:
> Reported-by: Sedat Dilek
> Suggested-by: Josh Poimboeuf
> Signed-off-by: Nick Desaulniers
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/a7032637b54186e5649917679727d7feaec932b1
cheers
On Mon, 2019-11-25 at 09:20:33 UTC, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The ISA_DMA_THRESHOLD variable is set by several platforms but never
> referenced.
> Remove it.
>
> Signed-off-by: Mike Rapoport
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/b77afad84e1eedc
On Sat, 2020-02-15 at 05:36:37 UTC, Leonardo Bras wrote:
> Before checking for cpu_type == NULL, this same copy happens, so doing
> it here will just write the same value to the t->oprofile_type
> again.
>
> Remove the repeated copy, as it is unnecessary.
>
> Signed-off-by: Leonardo Bras
Series
On Tue, 2019-11-26 at 13:51:14 UTC, "Gautham R. Shenoy" wrote:
> From: Shilpasri G Bhat
>
> Commit bf9571550f52 ("powerpc/powernv: Add support to clear sensor
> groups data") added a mechanism to clear sensor-group data via a sysfs
> interface. However, the ABI for that interface has not been
> d
On Mon, 2020-02-24 at 23:31:39 UTC, Michael Ellerman wrote:
> A while back Paul pointed out I'd been maintaining the tree more or
> less solo for over five years, so perhaps it's time to update the
> MAINTAINERS entry.
>
> Ben & Paul still wrote most of the code, so keep them as Reviewers so
> the
On Tue, 2020-02-25 at 17:35:10 UTC, Nicholas Piggin wrote:
> The code generation macro arguments are difficult to read, and
> defaults can't easily be used.
>
> This introduces a block where parameters can be set for interrupt
> handler code generation by the subsequent macros, and adds the first
On Thu, 2020-02-27 at 04:59:32 UTC, Michael Ellerman wrote:
> Relocatable kernel builds produce a warning about .gnu.hash being an
> orphan section:
>
> ld: warning: orphan section `.gnu.hash' from `linker stubs' being placed in
> section `.gnu.hash'
>
> If we try to discard it the build fails
On Fri, 2020-02-28 at 00:14:37 UTC, Christophe Leroy wrote:
> In order to allow splitting of ptrace depending on the
> different CONFIG_ options, create a subdirectory dedicated to
> ptrace and move ptrace.c and ptrace32.c into it.
>
> Signed-off-by: Christophe Leroy
Series applied to powerpc ne
On Thu, 2020-03-05 at 14:35:29 UTC, "Naveen N. Rao" wrote:
> The original commit/discussion adding -fno-dwarf2-cfi-asm refers to
> R_PPC64_REL32 relocations not being handled by our module loader:
> http://lkml.kernel.org/r/20090224065112.ga6...@bombadil.infradead.org
>
> However, that is now hand
On Fri, 2020-03-06 at 15:01:40 UTC, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= wrote:
> When a CPU is brought up, an IPI number is allocated and recorded
> under the XIVE CPU structure. Invalid IPI numbers are tracked with
> interrupt number 0x0.
>
> On the PowerNV platform, the interrupt number space
On Fri, 2020-03-13 at 11:20:19 UTC, Michael Ellerman wrote:
> We don't need the NULL check of np, the result is the same because the
> OF helpers cope with NULL, of_node_to_nid(NULL) == NUMA_NO_NODE (-1).
>
> Signed-off-by: Michael Ellerman
Series applied to powerpc next.
https://git.kernel.org
On Fri, 2020-03-20 at 10:32:42 UTC, "Aneesh Kumar K.V" wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
>
> Signed-off-by: Aneesh Kumar K.V
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/233ba5461838
On Wed, 2020-03-25 at 10:41:44 UTC, Nicholas Piggin wrote:
> Before:
>
> WARNING: CPU: 0 PID: 494 at arch/powerpc/kernel/irq.c:343
> CPU: 0 PID: 494 Comm: a Tainted: GW
> NIP: c001ed2c LR: c0d13190 CTR: c003f910
> REGS: c001fffd3870 TRAP: 0700 Tainted
On Wed, 2020-03-25 at 16:42:57 UTC, Fangrui Song wrote:
> .globl sets the symbol binding to STB_GLOBAL while .weak sets the
> binding to STB_WEAK. GNU as let .weak override .globl since binutils-gdb
> 5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996). Clang integrated
> assembler let the last win but
On Thu, 2020-03-26 at 18:49:16 UTC, Ganesh Goudar wrote:
> memcpy_mcsafe has been implemented for power machines which is used
> by pmem infrastructure, so that an UE encountered during memcpy from
> pmem devices would not result in panic instead a right error code
> is returned. The implementation
On Mon, 2020-03-30 at 08:03:56 UTC, Clement Courbet wrote:
> Declaring setjmp()/longjmp() as taking longs makes the signature
> non-standard, and makes clang complain. In the past, this has been
> worked around by adding -ffreestanding to the compile flags.
>
> The implementation looks like it onl
On Fri, 2020-03-27 at 09:53:19 UTC, Michael Ellerman wrote:
> We added a usage of try-run to pmu/ebb/Makefile to detect if the
> toolchain supported the -no-pie option.
>
> This fails if we build out-of-tree and the source tree is not
> writable, as try-run tries to write its temporary files to th
On Wed, 2020-04-01 at 02:38:36 UTC, Michael Ellerman wrote:
> In restore_tm_sigcontexts() we take the trap value directly from the
> user sigcontext with no checking:
>
> err |= __get_user(regs->trap, &sc->gp_regs[PT_TRAP]);
>
> This means we can be in the kernel with an arbitrary regs->tra
Free function kfree() already does NULL check, so the additional
check is unnecessary, just remove it.
Signed-off-by: Chen Zhou
---
arch/powerpc/kvm/book3s_hv_nested.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c
b/arch/powerpc/kvm/bo
Hi Michael,
On Wed, Apr 1, 2020 at 2:53 PM Michael Ellerman
wrote:
>
> On Mon, 2019-08-12 at 21:50:43 UTC, Nick Desaulniers wrote:
> > Reported-by: Sedat Dilek
> > Suggested-by: Josh Poimboeuf
> > Signed-off-by: Nick Desaulniers
>
> Applied to powerpc next, thanks.
Missed this one from August
'mem=" option is an easy way to put high pressure on memory during some
test. Hence after applying the memory limit, instead of total mem, the
actual usable memory should be considered when reserving mem for
crashkernel. Otherwise the boot up may experience OOM issue.
E.g. it would reserve 4G prio
On Thu, 2020-03-05 at 20:32 -0300, Leonardo Bras wrote:
> ---
> The new flag was already proposed on Power Architecture documentation,
> and it's waiting for approval.
>
> I would like to get your comments on this change, but it's still not
> ready for being merged.
New flag got approved on the d
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
LE
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
LE
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
LE
Balamuruhan S wrote:
Few ppc instructions are encoded in test_emulate_step.c, consolidate them to
ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this
consolidation.
Reuse the macros from ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 34 +
On 01/04/20 7:30 PM, Pingfan Liu wrote:
> 'mem=" option is an easy way to put high pressure on memory during some
> test. Hence after applying the memory limit, instead of total mem, the
> actual usable memory should be considered when reserving mem for
> crashkernel. Otherwise the boot up may e
Now that architectures provide arch_hugetlb_valid_size(), parsing
of "hugepagesz=" can be done in architecture independent code.
Create a single routine to handle hugepagesz= parsing and remove
all arch specific routines. We can also remove the interface
hugetlb_bad_size() as this is no longer use
With all hugetlb page processing done in a single file clean up code.
- Make code match desired semantics
- Update documentation with semantics
- Make all warnings and errors messages start with 'HugeTLB:'.
- Consistently name command line parsing routines.
- Check for hugepages_supported() befor
The routine hugetlb_add_hstate prints a warning if the hstate already
exists. This was originally done as part of kernel command line
parsing. If 'hugepagesz=' was specified more than once, the warning
pr_warn("hugepagesz= specified twice, ignoring\n");
would be printed.
Some architectur
The architecture independent routine hugetlb_default_setup sets up
the default huge pages size. It has no way to verify if the passed
value is valid, so it accepts it and attempts to validate at a later
time. This requires undocumented cooperation between the arch specific
and arch independent co
v2 -
Fix build errors with patch 1 (Will)
Change arch_hugetlb_valid_size arg to unsigned long and remove
irrelevant 'extern' keyword (Christophe)
Documentation and other misc changes (Randy, Christophe, Mina)
Do not process command line options if !hugepages_supported()
(Dave,
On 4/1/20 11:38 AM, Mike Kravetz wrote:
> With all hugetlb page processing done in a single file clean up code.
> - Make code match desired semantics
> - Update documentation with semantics
> - Make all warnings and errors messages start with 'HugeTLB:'.
> - Consistently name command line parsing
On Wed, Apr 1, 2020 at 1:49 AM Dan Williams wrote:
>
> On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva
> wrote:
> >
> > This driver exposes LPC memory on OpenCAPI pmem cards
> > as an NVDIMM, allowing the existing nvram infrastructure
> > to be used.
> >
> > Namespace metadata is stored on the
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch enables the OpenCAPI Persistent Memory driver, as well
> as DAX support, for the 'powernv' defconfig.
>
> DAX is not a strict requirement for the functioning of the driver, but it
> is likely that a user will want to create a
On Sun, Mar 29, 2020 at 10:53 PM Alastair D'Silva wrote:
>
> These values have been taken from the device specifications.
Link to specification?
Patchset adds json file metric support for the hv_24x7 socket/chip level
events. "hv_24x7" pmu interface events needs system dependent parameter
like socket/chip/core. For example, hv_24x7 chip level events needs
specific chip-id to which the data is requested should be added as part
of pmu events.
From: Jiri Olsa
Adding expr_ prefix for parse_ctx and parse_id,
to straighten out the expr* namespace.
There's no functional change.
Signed-off-by: Jiri Olsa
---
tools/perf/tests/expr.c | 4 ++--
tools/perf/util/expr.c| 10 +-
tools/perf/util/expr.h| 12 ++--
From: Jiri Olsa
Adding expr_scanner_ctx object to hold user data
for the expr scanner. Currently it holds only
start_token, Kajol Jain will use it to hold 24x7
runtime param.
Signed-off-by: Jiri Olsa
---
tools/perf/util/expr.c | 6 --
tools/perf/util/expr.h | 4
tools/perf/util/expr
This patch refactor metricgroup__add_metric function where
some part of it move to function metricgroup__add_metric_param.
No logic change.
Signed-off-by: Kajol Jain
---
tools/perf/util/metricgroup.c | 60 ---
1 file changed, 35 insertions(+), 25 deletions(-)
dif
Patch enhances current metric infrastructure to handle "?" in the metric
expression. The "?" can be use for parameters whose value not known while
creating metric events and which can be replace later at runtime to
the proper value. It also add flexibility to create multiple events out
of single me
Added test case for parsing "?" in metric expression.
Signed-off-by: Kajol Jain
---
tools/perf/tests/expr.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/perf/tests/expr.c b/tools/perf/tests/expr.c
index 516504cf0ea5..f9e8e5628836 100644
--- a/tools/perf/tests/expr.c
+++ b/t
Commit 54b5091606c18 ("perf stat: Implement --metric-only mode")
added function 'valid_only_metric()' which drops "Hz" or "hz",
if it is part of "ScaleUnit". This patch enable it since hv_24x7
supports couple of frequency events.
Signed-off-by: Kajol Jain
---
tools/perf/util/stat-display.c | 2 -
The hv_24×7 feature in IBM® POWER9™ processor-based servers provide the
facility to continuously collect large numbers of hardware performance
metrics efficiently and accurately.
This patch adds hv_24x7 metric file for different Socket/chip
resources.
Result:
power9 platform:
command:# ./perf s
On Tue, Mar 31, 2020 at 7:51 PM Segher Boessenkool
wrote:
>
> On Tue, Mar 31, 2020 at 08:56:23AM +0200, Christophe Leroy wrote:
> > While we are at it, can we also remove the 601 ? This one is also full
> > of workarounds and diverges a bit from other 6xx.
> >
> > I'm unable to find its end of lif
On power9, Virtual Accelerator Switchboard (VAS) allows user space or
kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE
instructions. NX provides various functionalities such as compression,
encryption and etc. But only compression (842 and GZIP formats) is
supported in L
This function allocates IRQ on a specific chip. VAS needs per chip
IRQ allocation and will have IRQ handler per VAS instance.
Signed-off-by: Haren Myneni
Reviewed-by: Cédric Le Goater
---
arch/powerpc/include/asm/xive.h | 9 -
arch/powerpc/sysdev/xive/native.c | 6 +++---
2 files ch
Kernel sets fault address and status in CRB for NX page fault on user
space address after processing page fault. User space gets the signal
and handles the fault mentioned in CRB by bringing the page in to
memory and send NX request again.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren
Allocate a xive irq on each chip with a vas instance. The NX coprocessor
raises a host CPU interrupt via vas if it encounters page fault on user
space request buffer. Subsequent patches register the trigger port with
the NX coprocessor, and create a vas fault handler for this interrupt
mapping.
Setup fault window for each VAS instance. When NX gets a fault on
request buffer, pastes fault CRB in the corresponding fault FIFO and
then raises an interrupt to the OS. The kernel handles this fault
and process faults CRB from this FIFO.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren
For each user space send window, register NX with fault window ID
and port value so that NX paste CRBs in this fault FIFO when it
sees fault on the request buffer.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-window.c | 15 +
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