Re: [PATCH V2] hwmon: (ibmpowernv) Add min/max attributes and current sensors

On 05/02/2017 10:34 AM, Guenter Roeck wrote: > On 05/01/2017 09:35 PM, Shilpasri G Bhat wrote: >> Hi Guenter, >> >> On 04/28/2017 06:59 PM, Guenter Roeck wrote: >>> On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote: Add support for adding min/max values for the inband sensors copied by

[PATCH v3 3/3] powerpc/mm/hugetlb: Add support for page accounting

Add __GFP_ACCOUNT to __hugepte_alloc() Signed-off-by: Balbir Singh --- arch/powerpc/mm/hugetlbpage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index a4f33de..94e56b1 100644 ---

[PATCH v3 2/3] powerpc/mm/book(e)(3s)/32: Add page table accounting

Add support in pte_alloc_one() and pgd_alloc() by passing __GFP_ACCOUNT in the flags Signed-off-by: Balbir Singh --- arch/powerpc/include/asm/nohash/32/pgalloc.h | 3 ++- arch/powerpc/mm/pgtable_32.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)

[PATCH v3 1/3] powerpc/mm/book(e)(3s)/64: Add page table accounting

Introduce a helper pgtable_gfp_flags() which just returns the current gfp flags and adds __GFP_ACCOUNT to account for page table allocation. The generic helper is added to include/asm/pgalloc.h and has two variants - WARNING ugly bits ahead 1. If the header is included from a module, no check for

[PATCH v3 0/3] Implement page table accounting for powerpc

(3e79ec7 arch: x86: charge page tables to kmemcg) added support for page table accounting). This patch is the second iteration to add support, in the earlier iteration only book3s 64 bit was supported. This iteration adds support for booke/3s/32 and 64 bit. There is some ugliness in this

Re: [PATCH V2] hwmon: (ibmpowernv) Add min/max attributes and current sensors

On 05/01/2017 09:35 PM, Shilpasri G Bhat wrote: Hi Guenter, On 04/28/2017 06:59 PM, Guenter Roeck wrote: On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote: Add support for adding min/max values for the inband sensors copied by OCC to main memory. And also add current(mA) sensors to the list.

Re: [PATCH V2] hwmon: (ibmpowernv) Add min/max attributes and current sensors

Hi Guenter, On 04/28/2017 06:59 PM, Guenter Roeck wrote: > On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote: >> Add support for adding min/max values for the inband sensors copied by >> OCC to main memory. And also add current(mA) sensors to the list. >> >> Signed-off-by: Shilpasri G Bhat

Re: [PATCH v4] cxl: mask slice error interrupts after first occurrence

Thanks for upadating the patch with review comments Alastair. Alastair D'Silva writes: > From: Alastair D'Silva > > In some situations, a faulty AFU slice may create an interrupt storm of > slice errors, rendering the machine unusable. Since these

[PATCH v3 10/11] soc/fsl/qbman: Add missing headers on ARM

From: Claudiu Manoil Unlike PPC builds, ARM builds need following headers explicitly: +#include for ioread32be() +#includefor udelay() Signed-off-by: Claudiu Manoil Signed-off-by: Roy Pledge ---

[PATCH v3 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

From: Madalin Bucur Signed-off-by: Madalin Bucur Signed-off-by: Claudiu Manoil [Stuart: changed to use ARCH_LAYERSCAPE] Signed-off-by: Stuart Yoder Signed-off-by: Roy Pledge ---

[PATCH v3 08/11] soc/fsl/qbman: add QMAN_REV32

From: Madalin Bucur Add revision 3.2 of the QBMan block. This is the version for LS1043A and LS1046A SoCs. Signed-off-by: Madalin Bucur Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++

[PATCH v3 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

Rework ioremap() for PPC and ARM. The PPC devices require a non-coherent mapping while ARM will work with a non-cachable/write combine mapping. Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/bman_portal.c | 12 +--- drivers/soc/fsl/qbman/qman_portal.c | 12

[PATCH v3 06/11] soc/fsl/qbman: Fix ARM32 typo

From: Valentin Rothberg The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'. Signed-off-by: Valentin Rothberg Signed-off-by: Claudiu Manoil Signed-off-by: Roy Pledge ---

[PATCH v3 09/11] soc/fsl/qbman: different register offsets on ARM

From: Madalin Bucur Signed-off-by: Madalin Bucur Signed-off-by: Claudiu Manoil Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/bman.c | 22 ++ drivers/soc/fsl/qbman/qman.c | 38

[PATCH v3 04/11] soc/fsl/qbman: Drop set/clear_bits usage

From: Madalin Bucur Replace PPC specific set/clear_bits API with standard bit twiddling so driver is portalable outside PPC. Signed-off-by: Madalin Bucur Signed-off-by: Claudiu Manoil Signed-off-by: Roy Pledge

[PATCH v3 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

Updates the QMan and BMan device tree bindings for reserved memory nodes. This makes the reserved memory allocation compatiable with the shared-dma-pool usage. Signed-off-by: Roy Pledge --- Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-

[PATCH v3 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

Use the shared-memory-pool mechanism for frame queue descriptor and packed frame descriptor record area allocations. Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/qman_ccsr.c | 138 +- drivers/soc/fsl/qbman/qman_priv.h | 4 +-

[PATCH v3 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

From: Claudiu Manoil Not relevant and arch dependent. Overkill for PPC. Signed-off-by: Claudiu Manoil Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/dpaa_sys.h | 4 1 file changed, 4 deletions(-) diff --git

[PATCH v3 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms

This patch series enables DPAA1 QBMan devices for ARM and ARM64 architectures. This allows the LS1043A and LS1046A to use QBMan functionality. Changes since v2: Fixed some misspellings Added 'no-map' constraint to device tree bindings Described ordering contraint on regions in the device tree

[PATCH v3 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

Use the shared-memory-pool mechanism for free buffer proxy record area allocation. Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++- drivers/soc/fsl/qbman/bman_priv.h | 3 +++ 2 files changed, 37 insertions(+), 1

Re: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

On 4/23/2017 9:47 PM, Scott Wood wrote: > On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote: >> Rework ioremap() for PPC and ARM. The PPC devices require a >> non-coherent mapping while ARM will work with a non-cachable/write >> combine mapping. >> >> Signed-off-by: Roy Pledge

Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO

On Mon, 2017-05-01 at 09:46 +0200, christophe leroy wrote: > > Le 30/04/2017 à 08:48, Scott Wood a écrit : > > On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote: > > > > > > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np) > > > > > >  

Re: [PATCH v2] powerpc/book3s: mce: Move add_taint() later in virtual mode.

Michael Ellerman writes: > Daniel Axtens writes: >>> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c >>> index a1475e6..b23b323 100644 >>> --- a/arch/powerpc/kernel/mce.c >>> +++ b/arch/powerpc/kernel/mce.c >>> @@ -221,6 +221,8 @@ static

[PATCH 1/1] powerpc/traps : Updated MC for E6500 L1D cache err

This patch updates the machine check handler of Linux kernel to handle the e6500 architecture case. In e6500 core, L1 Data Cache Write Shadow Mode (DCWS) register is not implemented but L1 data cache always runs in write shadow mode. So, on L1 data cache parity errors, hardware will automatically

[PATCH 2/2] powerpc/64s: Fix OPAL_CALL non-maskable interrupt reentrancy

OPAL_CALL uses SRR[01] with MSR_RI=1, which gets corrupted if there is an interleaving system reset or machine check interrupt. Use HSRR[01] instead, which does not require MSR_RI=0. Signed-off-by: Nicholas Piggin --- arch/powerpc/platforms/powernv/opal-wrappers.S | 6 +++---

[PATCH 1/2] powerpc/64s: Fix FIXUP_ENDIAN non-maskable interrupt reentrancy

FIXUP_ENDIAN uses SRR[01] with MSR_RI=1, which gets corrupted if there is an interleaving system reset or machine check interrupt. Set MSR_RI=0 before setting SRRs. The rfid will restore MSR. Signed-off-by: Nicholas Piggin --- arch/powerpc/boot/ppc_asm.h| 12

[PATCH 0/2] non maskable interrupt reentrancy fixes for OPAL

Hi, These fixes are more minimal, and split up properly since last post. Also accounted for Ben's comment of using HSRRs rather than disabling RI for OPAL_CALL. This will still increase cost of opal calls a bit due to new mtmsr in FIXUP_ENDIAN return. I have a few more patches that reduce

Re: [PATCH v2 2/3] powerpc/mm/book(e)(3s)/32: Add page table accounting

rove the system] > > url: > https://github.com/0day-ci/linux/commits/Balbir-Singh/powerpc-mm-book-e-3s-64-Add-page-table-accounting/20170501-143900 > base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next > config: powerpc-virtex5_defconfig (attached as .co

Re: [PATCH v2 2/3] powerpc/mm/book(e)(3s)/32: Add page table accounting

-table-accounting/20170501-143900 base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next config: powerpc-virtex5_defconfig (attached as .config) compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/01org/lkp

Re: [PATCH v2 2/3] powerpc/mm/book(e)(3s)/32: Add page table accounting

-table-accounting/20170501-143900 base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next config: powerpc-virtex5_defconfig (attached as .config) compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/01org/lkp

Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO

Le 30/04/2017 à 08:48, Scott Wood a écrit : On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote: This patch allows the use of IRQ to notify the change of GPIO status on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree. Ex: CPM1_PIO_C:

[PATCH v2] powerpc/8xx: Adding support of IRQ in MPC8xx GPIO

This patch allows the use of IRQ to notify the change of GPIO status on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree. Ex: CPM1_PIO_C: gpio-controller@960 { #gpio-cells = <2>; compatible = "fsl,cpm1-pario-bank-c";

[PATCH v2 3/3] powerpc/mm/hugetlb: Add support for page accounting

Add __GFP_ACCOUNT to __hugepte_alloc() Signed-off-by: Balbir Singh --- arch/powerpc/mm/hugetlbpage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index a4f33de..94e56b1 100644 ---

[PATCH v2 2/3] powerpc/mm/book(e)(3s)/32: Add page table accounting

Add support in pte_alloc_one() and pgd_alloc() by passing __GFP_ACCOUNT in the flags Signed-off-by: Balbir Singh --- arch/powerpc/include/asm/nohash/32/pgalloc.h | 3 ++- arch/powerpc/mm/pgtable_32.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)

[PATCH v2 1/3] powerpc/mm/book(e)(3s)/64: Add page table accounting

Introduce a helper pgtable_gfp_flags() which just returns the current gfp flags and adds __GFP_ACCOUNT to account for page table allocation. The generic helper is added to include/asm/pgalloc.h and has two variants - WARNING ugly bits ahead 1. If the header is included from a module, no check for

[PATCH v2 0/3] Implement page table accounting for powerpc

(3e79ec7 arch: x86: charge page tables to kmemcg) added support for page table accounting). This patch is the second iteration to add support, in the earlier iteration only book3s 64 bit was supported. This iteration adds support for booke/3s/32 and 64 bit. There is some ugliness in this