Hi Nicholas,
On Thu, May 16, 2019 at 04:13:17PM +1000, Nicholas Piggin wrote:
>
> > The motivation behind this patch was a HPC customer issue where they
> > were observing some CPUs in the core getting stuck at stop0_lite
> > state, thereby lowering the performance on the other CPUs of the core
Hi,
On Wed, May 15, 2019 at 01:15:52PM +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> The calls to arch_add_memory()/arch_remove_memory() are always made
> with the read-side cpu_hotplug_lock acquired via
> memory_hotplug_begin(). On p
t, good catch. Maybe oris r12,r12,0x3c is a better
> choice than that insrdi?
Perhaps oris is a better choice in this case since we are anyway
setting every bit in 42:45 range. Not sure if it will save any cycles,
but it will certainly reduce an instruction!
>
>
> >
> > Otherwise, the patch looks correct to me.
> > Reviewed-by: Gautham R. Shenoy
>
> Very much appreciate the reviews. I'm just getting some time to work on
> the winkle count patch, so I'll repost with your suggestions when that's
> done.
>
Looking forward to the new version!
> Thanks,
> Nick
>
--
Thanks and Regards
gautham.
From: "Gautham R. Shenoy"
Hi,
This patchset contains fixes to make CPU-Hotplug working on correctly
on POWER9 DD1 systems.
There are three patches in the series.
- The first patch adds a fallback mechanism for CPU-Hotplug when no
platform idle state is available.
- The second pat
From: "Gautham R. Shenoy"
Currently during idle-init on power9, if we don't find suitable stop
states in the device tree that can be used as the
default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default
stop state psscr to be used by power9_idle and deepest stop state
w
From: "Gautham R. Shenoy"
Currently, the powernv cpu-offline function assumes that platform idle
states such as stop on POWER9, winkle/sleep/nap on POWER8 are always
available. On POWER8, it picks nap as the default state if other deep
idle states like sleep/winkle are not available a
From: "Gautham R. Shenoy"
POWER9 platform can be configured to rebalance per-thread resources
within a core in order to improve SMT performance. Certain STOP
states can be configure to relinquish resources include some
hypervisor SPRs in order to enable SMT thread folding.
Due to rel
From: "Gautham R. Shenoy"
The various properties associated with powernv idle states such as
names, flags, residency-ns, latencies-ns, psscr, psscr-mask are
exposed in the device-tree as property arrays such the pointwise
entries in each of these arrays correspond to the properties o
Hi Nick,
Thanks for reviewing the patch.
On Wed, Mar 15, 2017 at 12:05:43AM +1000, Nicholas Piggin wrote:
> On Mon, 13 Mar 2017 11:31:27 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > Currently during idle-init on po
sleeps always require a state
> restore. This speedup is later re-introduced by counting per-core winkles
> and setting a bitmap of threads with state loss when all are in winkle.
>
Looks good to me.
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
--
Thanks and Regards
gautham.
On Tue, Mar 14, 2017 at 07:23:44PM +1000, Nicholas Piggin wrote:
> This reduces the number of nops for POWER8.
Nice!
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
> ---
> arch/powerpc/kernel/idle_book3s.S | 19 ---
> 1 file changed, 1
Hi Nick,
On Tue, Mar 14, 2017 at 07:23:46PM +1000, Nicholas Piggin wrote:
> POWER9 does not use this field, so it should be moved into the POWER8
> code. Update the documentation in the paca struct too.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/include/asm/paca.h | 12 ++
omic operations while we're here.
Looks good.
Reviewed-by: Gautham R. Shenoy
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/include/asm/cpuidle.h | 4 ++--
> arch/powerpc/kernel/idle_book3s.S | 33 +
> 2 files changed, 19 in
; - lbz r7,PACA_THREAD_MASK(r13)
> ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
> -lwarx_loop2:
> - lwarx r15,0,r14
> - andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
> + lbz r7,PACA_THREAD_MASK(r13)
Is reversing the order of loads into r7 and r14 intentional?
Other
p
> > > as the system reset interrupt does, rather than attempting to sleep
> > > again without going through the main idle path.
> > >
> > > Reviewed-by: Gautham R. Shenoy
> > > Signed-off-by: Nicholas Pig
Hi Nick,
On Tue, Mar 14, 2017 at 07:23:49PM +1000, Nicholas Piggin wrote:
> If not all threads were in winkle, full state loss recovery is not
> necessary and can be avoided. A previous patch removed this optimisation
> due to some complexity with the implementation. Re-implement it by
> counting
nding when the sleep/winkle instruction is executed.
>
> Signed-off-by: Nicholas Piggin
Acked-by: Gautham R. Shenoy
This fix should go into stable v4.8,v4.9 and v4.10.
Prior to commit 83289f909a72 ("powerpc/powernv: Rename idle_power7.S
to idle_book3s.S"), pnv_wakeup_tb_loss was exp
NV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
> + subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
> + beq 2f
> + ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
> +2:
> + /* Shift thread bit to winkle mask, then test if this thread is set,
>
From: "Gautham R. Shenoy"
Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self() which
transitions the CPU to the deepest available platform idle state to a
new function named pnv_cpu_offline() in powernv/idle.c. The rationale
behind this code movement is that the data r
From: "Gautham R. Shenoy"
POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread
waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the
core. Thus the HSPRG0 of a thread waking up from can contain the paca
pointer of its sibling.
This patch implements
From: "Gautham R. Shenoy"
Hi,
This is the second version of the patchset containing the fixes to
make CPU-Hotplug working on correctly on POWER9 DD1 systems.
The earlier version of this patchset can be found here:
https://lkml.org/lkml/2017/3/13/46
This patch addresses the feedbac
From: "Gautham R. Shenoy"
Currently, the powernv cpu-offline function assumes that platform idle
states such as stop on POWER9, winkle/sleep/nap on POWER8 are always
available. On POWER8, it picks nap as the default state if other deep
idle states like sleep/winkle are not available a
From: "Gautham R. Shenoy"
Currently during idle-init on power9, if we don't find suitable stop
states in the device tree that can be used as the
default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default
stop state psscr to be used by power9_idle and deepest stop state
w
Hi Nick,
On Mon, Mar 20, 2017 at 08:26:05PM +1000, Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 15:41:39 +0530
> Gautham R Shenoy wrote:
>
> > Hi Nick,
> >
> > On Mon, Mar 20, 2017 at 04:01:52PM +1000, Nicholas Piggin wrote:
> > > If not all threads were in
Hi Nick,
On Tue, Mar 21, 2017 at 02:35:17AM +1000, Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:15 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self
Hi,
On Tue, Mar 21, 2017 at 02:39:34AM +1000, Nicholas Piggin wrote:
> > @@ -241,8 +240,9 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
> > * The default stop state that will be used by ppc_md.power_save
> > * function on platforms that support stop instruction.
> > */
> > -u64
On Tue, Mar 21, 2017 at 02:59:46AM +1000, Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:18 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread
>
From: "Gautham R. Shenoy"
Hi,
This is the third version of the patchset containing the fixes to
make CPU-Hotplug working on correctly on POWER9 DD1 systems.
The earlier versions can be found here:
[v2] : https://lkml.org/lkml/2017/3/20/555
[v1] : https://lkml.org/lkml/2017/3/13/46
From: "Gautham R. Shenoy"
Currently, the powernv cpu-offline function assumes that platform idle
states such as stop on POWER9, winkle/sleep/nap on POWER8 are always
available. On POWER8, it picks nap as the default state if other deep
idle states like sleep/winkle are not available a
From: "Gautham R. Shenoy"
Currently during idle-init on power9, if we don't find suitable stop
states in the device tree that can be used as the
default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default
stop state psscr to be used by power9_idle and deepest stop state
w
From: "Gautham R. Shenoy"
POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread
waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the
core. Thus the HSPRG0 of a thread waking up from can contain the paca
pointer of its sibling.
This patch implements
From: "Gautham R. Shenoy"
Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self() which
transitions the CPU to the deepest available platform idle state to a
new function named pnv_cpu_offline() in powernv/idle.c. The rationale
behind this code movement is that the data r
plug, dying CPU is checked to see whether it is one of the
> designated cpus, if yes, next online cpu from the same chip (for nest
> units) is designated as new cpu to read counters. For this purpose, we
> introduce a new state : CPUHP_AP_PERF_POWERPC_NEST_ONLINE.
>
> Cc: Gautham R.
Hi Maddy, Hemant, Anju,
On Thu, Mar 16, 2017 at 01:05:02PM +0530, Madhavan Srinivasan wrote:
[..snip..]
> +
> +static void core_imc_change_cpu_context(int old_cpu, int new_cpu)
> +{
> + if (!core_imc_pmu)
> + return;
> + perf_pmu_migrate_context(&core_imc_pmu->pmu, old_cpu, n
ous ldbar value is written back to the LDBAR for that
> cpu.
>
> To register the hotplug functions for thread_imc, a new state
> CPUHP_AP_PERF_POWERPC_THREADIMC_ONLINE is added to the list of existing
> states.
>
> Cc: Gautham R. Shenoy
> Cc: Balbir Singh
> Cc: Benja
5c/0x78
>
> This patch fixes the bug by passing correct cpumask from
> powernv-cpuidle driver.
>
> Signed-off-by: Vaidyanathan Srinivasan
Reviewed-by: Gautham R. Shenoy
> ---
> drivers/cpuidle/cpuidle-powernv.c | 18 ++
> 1 file changed, 18 insertion
On Mon, Mar 27, 2017 at 10:43:44PM +1100, Michael Ellerman wrote:
> "Gautham R. Shenoy" writes:
>
> > diff --git a/arch/powerpc/platforms/powernv/idle.c
> > b/arch/powerpc/platforms/powernv/idle.c
> > index 419edff..f335e0f 100644
> > --- a/arch/powerpc
From: "Gautham R. Shenoy"
Hi,
This patchset contains three fixes required to get a deep stop state
that can lose the Hypervisor state to work correctly.
The first patch in the series uses the correct value for the
IDLE_THREAD_BITS on POWER8 which has 8 threads per core and on POWER9
From: "Gautham R. Shenoy"
This patch ensures that POWER8 and POWER9 processors use the correct
value of IDLE_THREAD_BITS as POWER8 has 8 threads per core and hence
the IDLE_THREAD_BITS should be 0xFF while POWER9 has only 4 threads
per core and hence the IDLE_THREAD_BITS should be 0x
From: "Gautham R. Shenoy"
On wakeup from a deep-stop used for CPU-Hotplug, we invoke
cur_cpu_spec->cpu_restore() which would set sane default values to
various SPRs including LPCR.
On POWER9, the cpu_restore_power9() call would would restore LPCR to a
sane value that is set at ea
From: "Gautham R. Shenoy"
The idle-exit code assumes that if Timebase is not lost, then neither
are the per-core hypervisor resources lost. This was true on POWER8
where fast-sleep lost only TB but not per-core resources, and winkle
lost both.
This assumption is not true for POWE
On Thu, Apr 13, 2017 at 08:00:47PM +1000, Michael Ellerman wrote:
> Michael Neuling writes:
>
> > On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote:
> >> From: "Gautham R. Shenoy"
> >>
> >> This patch ensures that POWER8 an
On Thu, Apr 13, 2017 at 04:55:45PM +1000, Michael Neuling wrote:
> On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > The idle-exit code assumes that if Timebase is not lost, then neither
> > are the per-core hy
On Thu, Apr 13, 2017 at 05:18:17PM +1000, Nicholas Piggin wrote:
> On Thu, 13 Apr 2017 16:27:34 +1000
> Michael Neuling wrote:
>
> > On Thu, 2017-04-13 at 14:12 +1000, Benjamin Herrenschmidt wrote:
> > > On Thu, 2017-04-13 at 09:28 +0530, Aneesh Kumar K.V wrote:
> > > > > #endif
> > > > >
Hi Nick,
On Fri, May 12, 2017 at 01:15:20AM +1000, Nicholas Piggin wrote:
> Fixes: a7cd88da97 ("powerpc/powernv: Move CPU-Offline idle state invocation
> from smp.c to idle.c")
> Cc: Gautham R. Shenoy
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/platform
From: "Gautham R. Shenoy"
commit 17ed4c8f81da ("powerpc/powernv: Recover correct PACA on wakeup
from a stop on P9 DD1") promises to set the NAPSTATELOST bit in paca
after recovering the correct paca for the thread waking up from stop1
on DD1, so that the GPRs can be corre
From: "Gautham R. Shenoy"
The current code in the cpuidle-powernv intialization only allows deep
stop states (indicated by OPAL_PM_STOP_INST_DEEP) which lose timebase
(indicated by OPAL_PM_TIMEBASE_STOP). This assumption goes back to
POWER8 time where deep states used to lose th
From: "Gautham R. Shenoy"
On Power9 DD1 due to a hardware bug the Power-Saving Level Status
field (PLS) of the PSSCR for a thread waking up from a deep state can
under-report if some other thread in the core is in a shallow stop
state. The scenario in which this can manifest is
From: "Gautham R. Shenoy"
The lower 8 bits of core_idle_state_ptr tracks the number of non-idle
threads in the core. This is supposed to be initialized to bit-map
corresponding to the threads_per_core. However, currently it is
initialized to PNV_CORE_IDLE_THREAD_BITS (0xFF). This is c
kshay Adiga
Signed-off-by: Gautham R. Shenoy
---
arch/powerpc/platforms/powernv/idle.c | 83 ++-
1 file changed, 52 insertions(+), 31 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/idle.c
b/arch/powerpc/platforms/powernv/idle.c
index 84eb9bc..4deac0d 1
From: "Gautham R. Shenoy"
On wakeup from a deep stop state which is supposed to lose the
hypervisor state, we don't restore the LPCR to the old value but set
it to a "sane" value via cur_cpu_spec->cpu_restore().
The problem is that the "sane" value doesn&#x
From: "Gautham R. Shenoy"
On POWER8, in case of
- nap: both timebase and hypervisor state is retained.
- fast-sleep: timebase is lost. But the hypervisor state is retained.
- winkle: timebase and hypervisor state is lost.
Hence, the current code for handling exit from a
From: "Gautham R. Shenoy"
Hi,
This patch series contains some of the fixes required for enabling
support for deep stop states such as STOP4 and STOP11 via CPU-Hotplug.
These fixes mainly ensure that some of the hypervisor resources which
are lost during the deep stop state are
Hi Nicholas,
On Tue, May 30, 2017 at 03:56:12PM +1000, Nicholas Piggin wrote:
> On Tue, 16 May 2017 14:19:43 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > The lower 8 bits of core_idle_state_ptr tracks the numb
On Tue, May 30, 2017 at 04:12:38PM +1000, Nicholas Piggin wrote:
> On Tue, 16 May 2017 14:19:44 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > On POWER8, in case of
> >- nap: both timebase and hypervisor stat
On Tue, May 30, 2017 at 04:17:31PM +1000, Nicholas Piggin wrote:
> On Tue, 16 May 2017 14:19:45 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > On wakeup from a deep stop state which is supposed to lose the
> > h
On Tue, May 30, 2017 at 05:13:57PM +1000, Nicholas Piggin wrote:
> On Tue, 16 May 2017 14:19:48 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > The current code in the cpuidle-powernv intialization only allows deep
>
On Tue, May 30, 2017 at 09:10:06PM +1000, Nicholas Piggin wrote:
> On Tue, 30 May 2017 16:20:55 +0530
> Gautham R Shenoy wrote:
>
> > On Tue, May 30, 2017 at 05:13:57PM +1000, Nicholas Piggin wrote:
> > > On Tue, 16 May 2017 14:19:48 +0530
> > > "Gautham R.
Hi Nick,
(Added Paul Mackerass to the Cc)
On Mon, Jun 12, 2017 at 09:58:22AM +1000, Nicholas Piggin wrote:
> This simplifies the asm and fixes irq-off tracing over sleep
> instructions.
>
> Also move powersave_nap check for POWER8 into C code, and move
> PSSCR register value calculation for POWER
Hi Nick,
On Mon, Jun 12, 2017 at 09:58:24AM +1000, Nicholas Piggin wrote:
> Before the cpuidle driver is enabled, provide a default idle
> function similarly to POWER7/8.
>
> This should not have much effect, because the cpuidle driver
> for powernv is mandatory, but if that changes we should hav
Hi Nick,
On Mon, Jun 12, 2017 at 09:58:25AM +1000, Nicholas Piggin wrote:
> When the CPU wakes from low power state, it begins at the system reset
> interrupt with the exception that caused the wakeup encoded in SRR1.
>
> Today, powernv idle wakeup ignores the wakeup reason (except a special
> ca
rect msgclr
> Different threads, same core: 315k/s 264k/s345k/s
> Different cores:235k/s 242k/s242k/s
>
> Net speedup is +10% for same core, and +3% for different core.
This is good speedup.
Reviewed-by: Gautham R. Shenoy
better with the return predictor.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
> ---
> arch/powerpc/kernel/exceptions-64s.S | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/exceptions-64s.S
> b/arch/
On Mon, Jun 12, 2017 at 09:58:30AM +1000, Nicholas Piggin wrote:
> In a busy system, idle wakeups can be expected from IPIs and device
> interrupts.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
> ---
> arch/powerpc/kernel/idle_book3s.S | 2 +-
&g
ime will not have to send an IPI.
>
> Expand the TIF_POLLING_NRFLAG coverage to as large as possible.
>
> Signed-off-by: Nicholas Piggin
Looks good. Were you able to see this make a difference in any of the
tests ?
Reviewed-by: Gautham R. Shenoy
> ---
> drivers/cpuidle/cpuidle
On Mon, Jun 12, 2017 at 09:58:32AM +1000, Nicholas Piggin wrote:
> Ensure these don't get put into bouncing cachelines.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
> ---
> drivers/cpuidle/cpuidle-powernv.c | 10 +-
> drivers/cpuidle
On Tue, Jun 13, 2017 at 12:46:02AM +1000, Nicholas Piggin wrote:
> Hi Gautham,
>
> Thanks for the reviews.
>
> On Mon, 12 Jun 2017 14:07:27 +0530
> Gautham R Shenoy wrote:
>
> > Hi Nick,
> >
> > (Added Paul Mackerass to the Cc)
> > On Mon, Jun
Hi Nick,
On Mon, Jun 12, 2017 at 09:58:29AM +1000, Nicholas Piggin wrote:
> Idle code now always runs at the 0xc... effective address whether
> in real or virtual mode. This means rfid can be ditched, along
> with a lot of SRR manipulations.
>
> In the wakeup path, carry SRR1 around in r12. Use m
From: "Gautham R. Shenoy"
On POWER9 DD1, in order to get around a hardware issue, we store in
every CPU thread's paca the paca pointers of all its siblings.
Move this code into pnv_alloc_idle_core_states() soon after the space
for saving the sibling pacas is allocated.
Signed-of
From: "Gautham R. Shenoy"
The details of the platform idle state are exposed by the firmware to
the kernel via device tree.
In the current code, we parse the device tree twice :
1) During the boot up in arch/powerpc/platforms/powernv/idle.c Here,
the device tree is parsed to obtain t
From: "Gautham R. Shenoy"
In this patch we define a new function named pnv_power8_idle_init().
We move the following code from pnv_init_idle_states() into this newly
defined function.
a) That patches out pnv_fastsleep_workaround_at_entry/exit when
no s
From: "Gautham R. Shenoy"
In the current idle initialization code, if there are failures in
pnv_probe_idle_states, then no platform idle state is
enabled. However, since the error is not propagated to the top-level
function pnv_init_idle_states, we continue initialization in this
From: "Gautham R. Shenoy"
Hi,
This patch set aims at cleaning up the powernv idle initialization
code mainly covering the following
a) Currently there is redundant code for parsing the device-tree for
idle states. We do it in two places, once during the platform idle
initializa
From: "Gautham R. Shenoy"
Currently, we use the opal call opal_slw_set_reg() to inform the that
the Sleep-Winkle Engine (SLW) to restore the contents of some of the
Hypervisor state on wakeup from deep idle states that lose full
hypervisor context (characterized b
Hello Nicholas,
On Fri, Jul 07, 2017 at 12:53:40AM +1000, Nicholas Piggin wrote:
> On Wed, 5 Jul 2017 22:08:12 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > The details of the platform idle state are exposed by
Hello Nicholas,
On Fri, Jul 07, 2017 at 01:01:49AM +1000, Nicholas Piggin wrote:
> On Wed, 5 Jul 2017 22:08:13 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > In the current idle initialization code, if there are
Hi Nicholas,
On Fri, Jul 07, 2017 at 01:06:46AM +1000, Nicholas Piggin wrote:
> On Wed, 5 Jul 2017 22:08:14 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > In this patch we define a new function named pnv_power8_idle_i
On Fri, Jul 07, 2017 at 01:16:09AM +1000, Nicholas Piggin wrote:
> On Wed, 5 Jul 2017 22:08:15 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > On POWER9 DD1, in order to get around a hardware issue, we store in
>
On Fri, Jul 07, 2017 at 01:29:16AM +1000, Nicholas Piggin wrote:
> On Wed, 5 Jul 2017 22:08:16 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > Currently, we use the opal call opal_slw_set_reg() to inform the that
&
On Sat, Jul 08, 2017 at 07:05:26PM +1000, Nicholas Piggin wrote:
> On Fri, 7 Jul 2017 23:07:10 +0530
> Gautham R Shenoy wrote:
>
> > On Fri, Jul 07, 2017 at 01:29:16AM +1000, Nicholas Piggin wrote:
> > > On Wed, 5 Jul 2017 22:08:16 +0530
> > > "Gautham R.
From: "Gautham R. Shenoy"
Hi,
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via C
From: "Gautham R. Shenoy"
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via C
From: "Gautham R. Shenoy"
Currently we use the stop-api provided by the firmware to program the
SLW engine to restore the values of hypervisor resources that get lost
on deeper idle states (such as winkle). Since the deep states were
only used for CPU-Hotplug on POWER8 systems, we wou
Hello Nicholas,
On Wed, Jul 19, 2017 at 12:14:12PM +1000, Nicholas Piggin wrote:
> Thanks for working on these patches. We really need to get this stuff
> merged and tested asap :)
>
> On Tue, 18 Jul 2017 19:58:49 +0530
[..snip..]
> > diff --git a/arch/powerpc/platforms/powernv/smp.c
> > b/arc
From: "Gautham R. Shenoy"
Hi,
This is the second iteration of the patchset to enable exploitation of
stop4 idle state on POWER9 via cpuidle.
The earlier version can be found here :
https://lkml.org/lkml/2017/7/18/691
The change from the first version is to the second patch titled
From: "Gautham R. Shenoy"
Currently we use the stop-api provided by the firmware to program the
SLW engine to restore the values of hypervisor resources that get lost
on deeper idle states (such as winkle). Since the deep states were
only used for CPU-Hotplug on POWER8 systems, we wou
From: "Gautham R. Shenoy"
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via C
Hi Nicholas, Michael,
On Wed, Jul 19, 2017 at 10:07:05PM +1000, Michael Ellerman wrote:
> Nicholas Piggin writes:
> >> diff --git a/arch/powerpc/kernel/asm-offsets.c
> >> b/arch/powerpc/kernel/asm-offsets.c
> >> index a7b5af3..0262283 100644
> >> --- a/arch/powerpc/kernel/asm-offsets.c
> >> +++
From: "Gautham R. Shenoy"
Hi,
This is the third iteration of the patchset to enable exploitation of
stop4 idle state on POWER9 via cpuidle.
The earlier version can be found here :
[v2]: https://lkml.org/lkml/2017/7/19/152
[v1]: https://lkml.org/lkml/2017/7/18/691
The changes
From: "Gautham R. Shenoy"
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via C
From: "Gautham R. Shenoy"
Currently we use the stop-api provided by the firmware to program the
SLW engine to restore the values of hypervisor resources that get lost
on deeper idle states (such as winkle). Since the deep states were
only used for CPU-Hotplug on POWER8 systems, we wou
Hi Michael,
On Wed, Dec 06, 2017 at 09:54:27PM +1100, Michael Ellerman wrote:
> Shilpasri G Bhat writes:
>
> > From: "Gautham R. Shenoy"
> >
> > Pstates are 8bit values but on POWER8 they are negative and on POWER9
> > they are positive. This patch adds
From: "Gautham R. Shenoy"
On POWERNV platform, Pstates are 8-bit values. On POWER8 they are
negatively numbered while on POWER9 they are positively
numbered. Thus, on POWER9, the maximum number of pstates could be as
high as 256.
The current code interprets pstates as a signed 8-bit v
Hi Balbir,
On Fri, Dec 08, 2017 at 02:44:40PM +1100, Balbir Singh wrote:
> On Thu, Dec 7, 2017 at 4:59 PM, Gautham R. Shenoy
> wrote:
> > From: "Gautham R. Shenoy"
> >
> > On POWERNV platform, Pstates are 8-bit values. On POWER8 they are
> > nega
From: "Gautham R. Shenoy"
On POWER8 and POWER9, the PMSR and the PMCR registers define pstates
to be 8-bit wide values. The device-tree exports pstates as 32-bit
wide values of which the lower byte is the actual pstate.
The current implementation in the kernel treats pstates as in
From: "Gautham R. Shenoy"
This is a third version of the patch to fix pstate related issues in
the powernv-cpufreq driver.
The previous versions can be found here:
[v2]: https://lkml.org/lkml/2017/12/7/1562
[v1]: https://lkml.org/lkml/2017/11/29/1338
On POWERNV platform, Pst
From: "Gautham R. Shenoy"
The code in powernv-cpufreq, makes the following two assumptions which
are not guaranteed by the device-tree bindings:
1) Pstate ids are continguous: This is used in pstate_to_idx() to
obtain the reverse map from a pstate to it's correspondi
From: "Gautham R. Shenoy"
On POWERNV platform, the fields for pstates in the Power Management
Status Register (PMSR) and the Power Management Control Register
(PMCR) are 8-bits wide. On POWER8 the pstates are negatively numbered
while on POWER9 they are positively numbered.
The d
Hi Balbir,
On Sun, Dec 17, 2017 at 02:15:25PM +1100, Balbir Singh wrote:
> On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy
> wrote:
> > From: "Gautham R. Shenoy"
> >
> > The code in powernv-cpufreq, makes the following two assumptions which
> > are no
Hi Balbir,
On Sun, Dec 17, 2017 at 02:17:02PM +1100, Balbir Singh wrote:
> On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy
[..snip..]
> >
> > -static inline int extract_pstate(u64 pmsr_val, unsigned int shift)
> > +static inline u8 extract_pstate(u64 pmsr_va
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