Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-07-15 Thread Athira Rajeev
> On 14-Jul-2020, at 11:38 AM, Michael Ellerman wrote: > > Athira Rajeev > writes: >>> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote: >>> >>> Hi Athira, >>> >>> Athira Rajeev writes: Sampled Instruction Event Register (SIER), is a PMU

Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-07-14 Thread Michael Ellerman
Athira Rajeev writes: >> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote: >> >> Hi Athira, >> >> Athira Rajeev writes: >>> Sampled Instruction Event Register (SIER), is a PMU register, >> ^ >>

Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-27 Thread Athira Rajeev
> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote: > > Hi Athira, > > Athira Rajeev writes: >> Sampled Instruction Event Register (SIER), is a PMU register, > ^ >

Re: [PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-19 Thread Michael Ellerman
Hi Athira, Athira Rajeev writes: > Sampled Instruction Event Register (SIER), is a PMU register, ^ that > captures architecture state for a given sample. And

[PATCH v3] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events

2020-03-18 Thread Athira Rajeev
Sampled Instruction Event Register (SIER), is a PMU register, captures architecture state for a given sample. And sier_user_mask defined in commit 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s") defines the architected bits that needs to be saved from the SPR. Currently all of