David Kanceruk wrote:
Hello Hans,
Our problem was with the FEC sending data with one or two
incorrect bytes when we switched from the MPC5200 to the MPC5200B. The
byte positions were always the same. The socket buffer has the correct
data before and after the DMA engine runs but the FEC
Hello Sylvain and David
I think it is a more basic problem then just cache. The setup is using
the psc2 and
psc3 in codec32 mode to communicate with a DSP. Because the MPC5200 had
problems with
the frame in slave mode (anomaly list), it is used in master mode, and
sends empty packets
of 256
Fix mpc5200 PSC SPI driver to actually work for CONFIG_PPC_MERGE
- s/mpc52xx/mpc5200/, as this was changed in device tree some time ago
- fix spi id detection
Signed-off-by: Domen Puncer [EMAIL PROTECTED]
---
drivers/spi/mpc52xx_psc_spi.c | 25 +++--
1 file changed, 11
Hi all,
maybe this is not the appropriate mailing list, sorry for that!
but, does anyone got a working BDI2000 configuration file + reg.
definitions for MPC8313E-RDB
to get access to NAND memory? I got one but there's only access to NOR
memory.
Many thanks in advance!
Best regards
Sylvain,
This is a shot in the dark but the fact that it is the last word that is
wrong reminds me of your question last week about the Gen_BD_TX
tasks:
2) From what I understand, this part process everything execpt the last
byte :
0xd9190300, /* LCDEXT: idx2 = idx2; idx2 var12;
David Brownell wrote:
On Wednesday 16 May 2007, Sylvain Munaut wrote:
Well, this comment is not about the patch but about the driver it self,
I didn't see it before today.
It merged earlier in the 2.6.22 cycle. If you don't have criticisms
about the patch itself, I'll forward it
On Wednesday 16 May 2007, Sylvain Munaut wrote:
Well, this comment is not about the patch but about the driver it self,
I didn't see it before today.
It merged earlier in the 2.6.22 cycle. If you don't have criticisms
about the patch itself, I'll forward it for merging after I get at
least
Fix Section mismatch warnings
Signed-off-by: Eugene Surovegin [EMAIL PROTECTED]
---
drivers/net/ibm_emac/ibm_emac_mal.c |3 +--
drivers/net/ibm_emac/ibm_emac_mal.h |3 +--
drivers/net/ibm_emac/ibm_emac_rgmii.c |2 +-
drivers/net/ibm_emac/ibm_emac_rgmii.h |2 +-
Original patch is from Jeff Haran [EMAIL PROTECTED] with my minor style
fixes. His comments follow:
The first problem was in the function that configures the PHY for
autonegotiation, genmii_setup_aneg(). The original code does a
read/modify/write of the autonegotiation advertizement register
Fix link speed detection change.
Thanks to Stefan Roese [EMAIL PROTECTED] for finding this bug.
CC: Stefan Roese [EMAIL PROTECTED]
Signed-off-by: Eugene Surovegin [EMAIL PROTECTED]
---
drivers/net/ibm_emac/ibm_emac_core.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
AFAIK, BDI2000 doesn't support NAND... of course you can load some code
which has NAND support into RAM (even u-boot if compiled properly) and
thus program NAND flash. But BDI firmware cannot program NAND directly.
Leonid.
From: [EMAIL PROTECTED]
I have a need to be able to read and write the gpio data registers PDATC
and PDATD from a user space program.
We have a userspace program that succesfully mmaps an offset in /dev/mem
and reads/writes registers in a CPLD at 0xFF00_.
The issue seems to be that when I mmap /dev/mem to
On May 16, 2007, at 4:59 PM, Charles Krinke wrote:
I have a need to be able to read and write the gpio data registers
PDATC
and PDATD from a user space program.
We have a userspace program that succesfully mmaps an offset in /
dev/mem
and reads/writes registers in a CPLD at
13 matches
Mail list logo
