On 8/2/07, John Williams <[EMAIL PROTECTED]> wrote:
> Hi,
>
> Any comments on the status/feasibility of suspend/resume for LinuxPPC on
> Xilinx devices?
Pretty much non-existant as far as status goes. Feasibility depends
entirely on what power management features the Xilinx silicon
supports. I h
Hi,
Any comments on the status/feasibility of suspend/resume for LinuxPPC on
Xilinx devices?
The only suspend-related traffic I see here in the last 12 months is for
the lite5200b board.
Any guesstimates of level of difficulty for such a task on Xilinx
PPC405? The core lite5200b patchset did
Hi, Ansari!
Ansari schrieb:
> Hi Koller & Kumar
>
> Thanks for ur reply.
>
> Is there a way to reset the full chip (MPC8560) whenever core reset
> occurs (using hardware or software) ??
I recommend you to have a look at i.e. the MPC8540ADS reference design
(as an example, the 8560 should be s
On Thu, Aug 02, 2007 at 12:23:31AM -0600, Grant Likely wrote:
> On the other hand there is PCI whose control registers fall within the
> SoC range; but the memory windows absolutely do not. If my flash
> argument holds water, then where does that leave PCI which kind of
> straddles the fence.
IMH
Yoni Levin wrote:
> myirq=74
OK, that's obviously not the problem then, but you still shouldn't rely
on them being equal.
Try dumping the PIC registers to see which interrupts (if any) are
actually pending.
-Scott
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L
myirq=74
-Original Message-
From: Scott Wood [mailto:[EMAIL PROTECTED]
Sent: Thursday, August 02, 2007 6:19 PM
To: Yoni Levin
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: GPIO interrupts on mpc8313e
Yoni Levin wrote:
> Yes, I removed the flag (0) and nothing change in both cases the
req
On Thursday 02 August 2007, Sergej Stepanov wrote:
> Add support for IDS8247 board from IDS GmbH, Germany
Hi Sergej,
Please split your patch into separate mails for the actual platform
support and for the device drivers.
One problem I see with the platform support is that the code is
not multip
Yoni Levin wrote:
> Yes, I removed the flag (0) and nothing change in both cases the request_irq
> return 0 which is good.
> Then I added enable_irq and I recived :
>
> Unbalanced enable for IRQ 74
Yeah, sorry, I misremembered what IRQF_DISABLED does. As Domen pointed
out, you need to pass myir
On Aug 2, 2007, at 1:48 AM, Ansari wrote:
> Hi Koller & Kumar
>
> Thanks for ur reply.
>
> Is there a way to reset the full chip (MPC8560) whenever core
> reset occurs (using hardware or software) ??
what do you mean by core reset?
- k
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Linuxppc
Hello!
Add support for IDS8247 board from IDS GmbH, Germany
Regards
Sergej Stepanov.
---
diff -ruN linux-2.6.22.1_orig/arch/powerpc/boot/dts/mpc8247ids.dts
linux-2.6.22.1_ids8247/arch/powerpc/boot/dts/mpc8247ids.dts
--- linux-2.6.22.1_orig/arch/powerpc/boot/dts/mpc8247ids.dts1970-01-01
01:
Hi all,
I've continued my tests with the TQM5200. It appears that the
"Warning: kfree_skb on hard IRQ c008ecfc" errors are happening
because ppp_async_encode calls kfree_skb. I think this in itself is
not a problem, but when I googled for "ppp_async_encode hard IRQ", I found this:
http://search.l
Yes, I removed the flag (0) and nothing change in both cases the request_irq
return 0 which is good.
Then I added enable_irq and I recived :
Unbalanced enable for IRQ 74
[ cut here ]
Badness at c0043578 [verbose debug info unavailable]
Call Trace:
[C76C9D00] [C0008648] show
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