> "Jens" == Jens Gehrlein <[EMAIL PROTECTED]> writes:
Jens> Hi,
Jens> on our board a SMSC LAN9215i is connected to an i.MX31 ARM
Jens> processor. My hope is to get the smc911x driver run on this chip. The
Jens> LAN921x data sheets say that existing 911x drivers should work.
Why are you as
Hi Peter,
thank you for responding.
Peter Korsgaard schrieb:
"Jens" == Jens Gehrlein <[EMAIL PROTECTED]> writes:
Jens> Hi,
Jens> on our board a SMSC LAN9215i is connected to an i.MX31 ARM
Jens> processor. My hope is to get the smc911x driver run on this chip. The
Jens> LAN921x data sheets
> "Jens" == Jens Gehrlein <[EMAIL PROTECTED]> writes:
Hi,
Jens> on our board a SMSC LAN9215i is connected to an i.MX31 ARM
Jens> processor. My hope is to get the smc911x driver run on this chip. The
Jens> LAN921x data sheets say that existing 911x drivers should work.
>>
>> Why are you
Hi,friends,
I designed my MPC8360E board with 1GBytes DDR-1 memory, I built two demo
boards, one is 533/266/400, the other is 660/330/400. The lower frequancy board
is
no problem for our program, but the higher frequency board is always problem
about
the data transmit on ethernet.
I want t
Hello,
This is my first post to the linuxppc-embedded list. Please forgive me
for jumping in late onto the CPU15 workaround discussions, but my
company is very interested in finding an efficient fix for this silicon
errata on our devices.
I applied the patch submitted by Scott Wood to our pa
Hi Swamy,
I have seen this sometime before I think, but don't remember why.
I see that udelay depends on loops_per_jiffy, have you looked to see
what value it is? Maybe it's garbage and some large value?
Have you tried dumping the __log_buf to understand how far it got thru
booting the kernel be
I am having some trouble using the xilinx_hwicap driver in Linux.
I am using version 2.6.24-rc8-xlnx of the Linux kernel from the Xilinx
GIT repository.
The xilinx_hwicap driver is statically compiled in - not a loadable module.
I am using the opb_hwicap device on a V4FX60 FPGA, Linux running on th
I designed my MPC8360E board with 1GBytes DDR-1 memory, I built two demo
boards, one is 533/266/400, the other is 660/330/400. The lower frequancy board
is
no problem for our program, but the higher frequency board is always problem
about
the data transmit on ethernet.
I want to test 1GBytes
On May 14, 2008, at 10:52 AM, Ben Gardiner wrote:
So there likely are reasons why the following is not possible:
That's way too much code for a tlb exception handler.
From a system resource perspective, you are much better
off with a small and efficient piece of tlb loading code,
always inval
I bet you're using ARCH ppc...
It looks like in arch/ppc/syslib/virtex_devices.c:
#define XPAR_HWICAP(num) { \
.name = "xilinx_icap", \
Should probably be:
#define XPAR_HWICAP(num) { \
.name = "icap", \
now.
Can you make this change locally and verify that it solves the probl
Steve,
Yes, this fixed that problem. the following is now printed when
booting the kernel.
[5.866230] icap icap.0: Xilinx icap port driver
[5.866401] icap icap.0: ioremap 4020 to c500 with size 1
The icap is at address 0x4020 on my system, so that seems correct.
However,
OK, that's progress. The next thing I'd check is that you are *not*
using the JTAG configuration mode, as this disables the ICAP. You can
also try turning on the DEBUG flags in the driver itself. During open()
the driver attempts to read the IDCODE from the hwicap to get it back to
an initial
Dan Malek wrote:
On May 14, 2008, at 10:52 AM, Ben Gardiner wrote:
So there likely are reasons why the following is not possible:
That's way too much code for a tlb exception handler.
From a system resource perspective, you are much better
off with a small and efficient piece of tlb loading
--- ¹ù¾¢ <[EMAIL PROTECTED]> wrote:
> Hi,friends,
>I designed my MPC8360E board with 1GBytes DDR-1 memory, I
> built two demo
> boards, one is 533/266/400, the other is 660/330/400. The
> lower frequancy board is
> no problem for our program, but the higher frequency board is
> always problem
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