RE: Reading and writing from/to VME device

2007-03-29 Thread Martin, Tim
>But when I try to configure it with outWinCfgADC.zlatedAddrL = 0xA000, >when I run the programm I get an errno 29 (Invalid argument) from ioctl(). >In fact if I set the xlatedAddrL to some value smaller that 0x1 I get this >error. Here's my most recent configuration: The VME device driver ha

RE: Reading and writing from/to VME device

2007-03-27 Thread Martin, Tim
>I tried to assign it to some other value (just a guess like 0x1000, which I think is > 0x1000 in A16), and then try to read through as many addresses as the size of the > window contains. Your code indicated said you're using A24 addressing. You should assign an A24 address. > I ge

RE: Reading and writing from/to VME device

2007-03-26 Thread Martin, Tim
> I'm using the MVME6100 board with the Motorola driver for linux v3.5 (kernel 2.6.15). I'm not sure what a "Linux v3.5" is - Montavista? There are patches available from Motorola to the vanila kernel if you're interested in using something newer than 2.6.15. > I try to access the CSR registers

RE: UartLite for MontaVista - virtex4

2007-03-14 Thread Martin, Tim
> Could you tell me where exactly to get the "xuartlite_serial.c" ? > > I could not find "xuartlite_serial.c" in the drivers folder generated by EDK . > (\ppc405_0\libsrc\linux_mvl31_v1_01_b\linux\drivers\char\xilinx_uartlite ) Here's the relevant snippet for xulite_send_handl

RE: UartLite for MontaVista - virtex4

2007-03-14 Thread Martin, Tim
> Xilinx OS Independent Code XAssert: xuartlite.c:195 > Code may crash due to unhandled errors. > Xilinx OS Independent Code XAssert: xuartlite.c:195 > Code may crash due to unhandled errors. > Xilinx OS Independent Code XAssert: xuartlite.c:195 > Code may crash

RE: debugging custom Xilinx boot loader with abatron and Montavistadevrocket

2007-02-24 Thread Martin, Tim
> 1) In DevRocket, what kind of project do you choose to debug an > externally build .elf file? > MontaVista support engineers had no clue. Not sure about DevRocket specifically, but in Eclipse you would choose a C application with external makefile. In Eclipse 3.1 (with CDT) its specifically cal

RE: Stupid Telnet Question

2007-01-03 Thread Martin, Tim
> -Original Message- > From: Erik Habbinga [mailto:[EMAIL PROTECTED] > Sent: Wednesday, January 03, 2007 10:27 AM > To: Martin, Tim > Subject: Re: Stupid Telnet Question > > Tim, >Did you ever figure out how to get telnet to work with > ELDK 4.0? I&#

Stupid Telnet Question

2006-09-10 Thread Martin, Tim
I'm using ELDK 4.0 on a custom PPC74xx board, and NFS mounting the root file system. When I use the default NFS directory (e.g. /opt/eldk_4.0/ppc_74xx) read-write, I can telnet into the board fine (after modifying /etc/xinetd.d/telnet of course). But this default directory is overkill for my futu

Stupid Telnet Question

2006-09-10 Thread Martin, Tim
I'm using ELDK 4.0 on a custom PPC74xx board, and NFS mounting the root file system. When I use the default NFS directory (e.g. /opt/eldk_4.0/ppc_74xx) read-write, I can telnet into the board fine (after modifying /etc/xinetd.d/telnet of course). But this default directory is overkill for my futu

RE: MAC driver issue

2006-09-06 Thread Martin, Tim
> > > I have no doubt it is with the driver. I am somewhat > fortunate in > > this instance that I have a nearly identical setup - this > is an FPGA > > based system > > I can swap the FPGA firmware, get an almost identical > kernel with > > a slightly different NIC, and everything

MAC driver issue

2006-09-06 Thread Martin, Tim
> > > I have no doubt it is with the driver. I am somewhat > fortunate in > > this instance that I have a nearly identical setup - this > is an FPGA > > based system > > I can swap the FPGA firmware, get an almost identical > kernel with > > a slightly different NIC, and everything

Cache coherency question

2006-08-25 Thread Martin, Tim
> > Tim> I'm using an MVME6100 with Linux 2.6.14 and experiencing what I > Tim> think is a cache coherency problem. An external PCIX master > Tim> performs a DMA transfer of a well known data pattern into SDRAM, > Tim> but when the device driver goes to look at the data it is mostly > Tim> ok

Cache coherency question

2006-08-24 Thread Martin, Tim
I'm using an MVME6100 with Linux 2.6.14 and experiencing what I think is a cache coherency problem. An external PCIX master performs a DMA transfer of a well known data pattern into SDRAM, but when the device driver goes to look at the data it is mostly okay, but occasionally has garbage. I'm all

Debugging with no serial port

2006-08-11 Thread Martin, Tim
> > > > I tried this as well and have the same GDB synchronization > problem e.g. > > > > break log_stuff > > commands > >silent > >if (variable_logging_enabled) > > printf "(%d,%d)\n",stuff1_variable,stuff2_variable > >end > >cont > > end > > > That's too bad. I wo

Debugging with no serial port

2006-08-10 Thread Martin, Tim
Ben, > How about something a bit simpler like running gdb within a 'script' context, > which will log your session to a file. Get gdb to print the variables to the screen > (using 'print' or whatever), wrap your data with easily searchable characters > (eg. ***data1 data2 data3***), then f

Debugging with no serial port

2006-08-10 Thread Martin, Tim
>> Second question would be - is there an easier way to accomplish what >> I'm trying to do, which is basically emulate a serial port with GDB. > > Use NetConsole or remotey log it with syslog... > I guess I wasn't clear in the problem statement - this target doesn't have a serial port, an e

Debugging with no serial port

2006-08-10 Thread Martin, Tim
This may be more of a question for GDB folks...but I'll post it here because it relates to embedded systems as well. I'm trying to validate some signal processing software on an embedded Virtex4 PowerPC 405. Basically, the validation consists of calling functions and looking at their outputs. O

Xilinx PIC and kernel interrupt handler

2006-07-31 Thread Martin, Tim
Regarding the IVR patch: Have you seen this bug in practice, or just from examining the code? The reason I ask is I've recently looked at this myself, and was under the impression that "w" is the width of the data bus (DB) (per page 9 of dcr_intc.pdf). So regardless of how many interrupt sources

caches on Virtex 4

2006-07-26 Thread Martin, Tim
Robert, There are several registers/etc that affect the caches on the Virtex4 PPC core. Step 1 - Make sure your FPGA is configured to have caches in the memory regions you're interested in caching. Your FPGA designer should have done this in the EDK (check options in the MHS file). Step 2 - Mak

Linux on Virtex4

2006-06-20 Thread Martin, Tim
Rick, Yes, I did make sure this patch was applied. Thanks! Tim > -Original Message- > From: Rick Moleres [mailto:rick.moleres at xilinx.com] > Sent: Tuesday, June 20, 2006 8:30 AM > To: Martin, Tim; linuxppc-embedded at ozlabs.org > Subject: RE: Linux on Virtex4 > &

Linux on Virtex4

2006-06-19 Thread Martin, Tim
I have been working with a small module made by Memec/Avnet (FX12MM1-BASE) that has a Virtex-4 FX12 with some DDR SDRAM, a Gigabit Ethernet PHY, some FLASH, etc. I am using EDK 8.1 and generated the BSP for MontaVista 3.1 "preview kit" (which is based on the 2.4.20 kernel). This works, but occasio

Jumbo ethernet frames on MVME6100

2006-06-09 Thread Martin, Tim
I'm using Linux 2.6.6 with the Motorola Computer Group patch for the MVME6100 available at https://mcg.motorola.com/cfm/templates/swDetails.cfm?PageID=704&Software ID=6&ProductID=202 and compiling with GCC from ELDK 3.1.1, although using the userspace module utils (e.g. insmod) from ELDK 4.0. Th

Debugging tools

2006-06-08 Thread Martin, Tim
> > I was hoping to be able to bring up gdb, download an elf file to the > target and step through a program to see where it is going off the rails. > Assuming you have the Xilinx EDK tools installed, there is a program called xmd that acts as a standalone debugger or can communicate with gd

MPC85xx PCI transfer disconnect

2006-06-02 Thread Martin, Tim
More information... > > Did you enable Memory Read Multiple command of your PCI master? > > Thanks for the clue. I'm trying to figure out how to do this. The PCI > master is a Tundra TSI148 VME-PCI bridge. The documentation says it > supports the PCI read multiple cycle, but so far I haven't f

MPC85xx PCI transfer disconnect

2006-06-02 Thread Martin, Tim
a 32 byte or 64 byte read, the MPC85xx does not disconnect the transfer. Tim > -Original Message- > From: Liu Dave-r63238 [mailto:DaveLiu at freescale.com] > Sent: Thursday, June 01, 2006 8:52 PM > To: Martin, Tim; linuxppc-embedded at ozlabs.org > Subject: RE: MPC85xx PCI

MPC85xx PCI transfer disconnect

2006-06-01 Thread Martin, Tim
I know this is probably a question for Freescale directly, but I thought I would post here to see if anyone else has seen similar issues with the MPC85xx PCI under Linux. I'm using a Freescale MPC85xx (8541) processor and seeing an extreme slowness to the PCI bus. I'm attemping to do 2048 byte PC

PPC Linux support for Tundra TSI148

2006-04-26 Thread Martin, Tim
abs.org] On Behalf > Of Gerhard Jaeger > Sent: Wednesday, April 26, 2006 12:26 AM > To: linuxppc-embedded at ozlabs.org > Subject: Re: PPC Linux support for Tundra TSI148 > > On Wednesday 26 April 2006 01:47, Martin, Tim wrote: > > Does anyone out there have any real world meas

PPC Linux support for Tundra TSI148

2006-04-25 Thread Martin, Tim
Does anyone out there have any real world measured performance of a Linux PowerPC (kernel module + user space application) doing 2eSST VME transfers with the Tundra TSI148 chipset? Tundra has a Linux driver available for the Motorola MVME6100 , but told me they don't have any performance data avai

question about Linux 2.6 with Xilinx ML-403

2006-04-12 Thread Martin, Tim
> > > > Ethernet? (Hard-Core PLB TEMAC?, Soft-Core PLB EMAC? Localink TEMAC? Is > > 10/100/1000 supported, or is there only 1 rate e.g. 1000 supported?) > > No. I've ported the 2.4 driver, but I haven't got permission to > release it yet. (I'm a contractor; I don't own any of the work I do) >

question about Linux 2.6 with Xilinx ML-403

2006-04-12 Thread Martin, Tim
Grant, I know I could probably figure this out by looking at the GIT tree directly (which I'm planning to do) but could you summarize how much (which devices) of the ML-403 is supported by your patches? Serial? (which Xilinx core) Ethernet? (Hard-Core PLB TEMAC?, Soft-Core PLB EMAC? Localink TEM

POSIX High Resolution Timers in LinuxPPC 2.4

2005-12-16 Thread Martin, Tim
Could someone give me a brief history lesson on POSIX high resolution timers (e.g. timer_create() function) implemented in the Linux kernel on the PowerPC 405 architecture? Specifically: Confirm they are in the mainline 2.6 kernel now (e.g. kernel.org)? Were they ever a part of the "mainli

MPC860 CP / CPM Misbehaving

2005-05-25 Thread Martin, Tim
An update (and solution) to the problem I was having...Thanks to everyone who sent me suggestions! > I'm using a custom MPC860 based embedded board and having problems with SCC1 > and SMC1 reception. I have SCC1 setup in ethernet mode, and SMC1 setup in > UART mode. The general problem manifests

MPC860 CP / CPM Misbehaving

2005-05-17 Thread Martin, Tim
> descriptors (BDs) from the CPM with the OV bit set (bit 14 of the RxBD > status/control field, "Overrun. Set when a receiver overrun > occurs during > reception"). > - SDRAM setup. If ORx(BIH)=1 makes the problem go away, your burst setup or the /TA pullup is broken. NB: Neither the SCC > nor

MPC860 CP / CPM Misbehaving

2005-05-13 Thread Martin, Tim
so it does sound like a likely candidate. Thanks for the tip. Tim -Original Message- From: wd at denx.de [mailto:[EMAIL PROTECTED] Sent: Friday, May 13, 2005 4:42 PM To: Martin, Tim Cc: 'linuxppc-embedded at ozlabs.org' Subject: Re: MPC860 CP / CPM Misbe

MPC860 CP / CPM Misbehaving

2005-05-13 Thread Martin, Tim
Not so much a linux question, as a general MPC860 question, but maybe someone out there can help. I'm using a custom MPC860 based embedded board and having problems with SCC1 and SMC1 reception. I have SCC1 setup in ethernet mode, and SMC1 setup in UART mode. The general problem manifests itself

linuxppc_2_4_devel on walnut

2001-11-07 Thread Martin, Tim
You can leave the default value of ic_enable at 0 and enter ip=bootp as part of your boot prompt. Tim -Original Message- From: Wright, David [mailto:[EMAIL PROTECTED] Sent: Wednesday, November 07, 2001 9:47 AM To: Kenneth Johansson; linuxppc-embedded at lists.linuxppc.org; akuster at mvi

Multiple MPC8xx SCC ethernets

2001-10-26 Thread Martin, Tim
I'm looking for patches to allow multiple SCC based ethernets on MPC8xx based boards. The 2.4 kernel releases only allow selection of either SCC1, SCC2, or SCC3, but not all three at the same time. Twice in the last few months, there's been a thread discussing this but I've never seen any code p