Large Page Support, 2.6 kernel , PPC440

Morris, A long time ago, I did this for a 405 and it involves much more than just changing the page shift. >From my memory, I will give you what I think you have to do. 1)you must go into tlb handling code and change it. That is in the header file 44x.S i beleive. 2)You have to change the pte di

where do applications get loaded in virtual memory on a 4xx?

I would like to know where in virtual memory application get loaded. I can do an NM and see the address in an a.out file? How do these address actually translate to 4xx virtual address? thanks Chip -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org

cross tools for the 440gp

are there any prebuild cross compilers for the 440gp processors that would compile a 2.6 kernel? If so, could I get some pointer to where they are? Thanks Chip

cross tools for the 440gp

are there any prebuild cross compilers for the 440gp processors that would compile a 2.6 kernel? If so, could I get some pointer to where they are? Thanks Chip

framebuffer access in little endian mode

Laurent, One thought would be to modify the pte entries to support little endian and have an IO_Remap little endian. (To those who think this is herasy or what ever, I accept you critisisms.) Any body else out there with better, and I know there must be better solutions? Chip Laurent Mohin

IDE driver support in PPC440

I am using the MontaVista 2.1 port and the Promise IDE works perfectly. I just plugged it in and it just ran. Chip -- Original Message -- From: Xupei Liang <[EMAIL PROTECTED]> Date: Wed, 14 May 2003 08:20:11 -0700 (PDT) > >Hi, Eugene, > >The IRQ7 is se

Disabling data cache

Yes, I gave it a breif test and it did not work and I did not have time to debug it. Chip ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Possible bug in flush_dcache_all on 440GP

This comment is from Thomas Sartorius, Eugene is correct about the "generic" way requiring that you load twice as many memory locations as would fit in the cache, in order to guarantee that any previous "dirty" contents get written to memory and removed from the cache. Note that his second sugg

DBCR0 reset?

Hollis, The OS does this. I send you the info on how to disable it tommorrow. Chip Hollis Blanchard wrote: > Has anyone had problems with hardware breakpoints from external > debuggers? I'm using RISCWatch, which sets DBCR0 and IAC1 for me (yes > I've verified that). I'm then using 'echo > /pr

very minor 405GP and 405GPr PCI difference

David, Let me expain On the 405gp, the PMM0 enable is hardwired 1 and cannot be overwritten by software. This makes the PMM0 region permantly enabled on the 405GP. I cannot be turned off. When the technology port was done, the design of the PCI was changed slightly because the designer made

very minor 405GP and 405GPr PCI difference

The MontVista Linux disables disable PMM1, which is correct. It then writes a 0 PMM0 enable bit, which on the 405gp is OK because the enable bit is hardwired to a 1. ON the 405gpr, the bit is writeable and this then disables PMM0. The correct action is to write a 1 to the PMM0 enable bit on bot

Riscwatch Probe

Kenneth, Try compiling with -dwarf2. We have no problem with symbolic debugwith riscwatch here. You will also need to set you srchpath to inclulde the .o file that contain the debug info Chip Kenneth Johansson @lists.linuxppc.org on 10/21/2002 03:38:47 AM Sent by:owner-linuxppc-embed

Riscwatch Probe

Aman, As long as PPCBOOT does note do anything with the DBCR registers, the answer is yes. Chip Aman wrote: > Hi All > > Can we use Riscwatcg Probe from IBM to debug PPCboot code. > > Thanking you in advance > Regards > Aman > > > > > . > ** Sent via the linuxppc-embedded mail list. See http:

How to change endian attribute for a memory region

No has written an IOremap_LE. Chip "Laurent Mohin" @lists.linuxppc.org on 10/15/2002 11:00:02 AM Sent by:owner-linuxppc-embedded at lists.linuxppc.org To:Ralph Blach/Raleigh/IBM at IBMUS cc:Matt Porter , linuxppc-embedded at lists.linuxppc.org Subject:Re: How

How to change endian attribute for a memory region

OK, I know this is absolute HERESY for all you out there, and would never be supported in the kernel tree, and probably with very good reasons, but I'll mention it anyway. ON the 405 and the 440 class processors, there is an endian bit in the TLB which would make a 4k region little endian. To u

very minor 405GP and 405GPr PCI difference

Yesterday I discovered a minor 405GP vs 405GPr PCI difference. IN the 405GP the ptm1ms bit 31, the enable bit for the region is set to 1 by the hardware and cannot be written. On the 405GPr the bit is writable and this makes necessitates a change in walnut.c In walnut.c there is the line out_le

Changes to "The plan"

Armin It has always been my contention the the 4xx should be organized in the following structure Core Chip board This would tree would then reflect the reallity of chip design methodology. the 405 now has many variants so it would be 405 Core Chip 405CR 405GP Board

consistent_alloc() revisited

Dan and Matt I agree with you 100% Chip -- Forwarded by Ralph Blach/Raleigh/IBM on 07/16/2002 12:13 PM --- Matt Porter @lists.linuxppc.org on 07/16/2002 11:27:26 AM Sent by:owner-linuxppc-embedded at lists.linuxppc.org To:Dan Malek cc

consistent_alloc changes for 4xx/8xx

I just looked closely at the code for pinned tlb's head_4xx.S and there needs to be a fix. /* Load up the kernel context */ 2: SYNC /*For all PTE updates to finish */ tlbia sync This is incorrect for a the pinned kernel configuration and because it would invalidate the pinned tlb's

consistent_alloc changes for 4xx/8xx

I have just looked at the code for pinning tlbs and have several suggestions for improvement. 1)put the tlb_4xx_index in the first 64 k of memory. 2)add a tlb_4xx_watermark in the same cache line as the index register. Next, change the tlb miss code for pinning to li r22, tlb_4xx_index at

consistent_alloc changes for 4xx/8xx

> On the IBM book E part, __va()/__pa() will have to be obsoleted. The > address space is > 36 bits. Better now than later. These macros are not used on I/O space addresses, and would continue to work properly on the Book E parts when used as intended. In fact they are still used in all kernel

consistent_alloc changes for 4xx/8xx

Dan, here are my responces. >>Another, more challenging, situation also exists because you can't use >>the __va()/__pa() macros on the addresses returned from consistent_alloc (). >>On the 4xx/8xx, the virt_to_* macros will call iopa() which will track down >>the real physical address in the pa

Organisation of 4xx initialization code

Just a note that might influence you. The sprs of each 405 will be the same, but there is NO gurantee that the DCR, any of them look anything like any other DCR in any other DCR. I suggest core, chip, and then platform specfic. Chip Paul Mackerras wrote: > Tom Rini writes: > > > > No need - t

Errata 67/77 / walnut bugs (was: Re: Erratum 51 bugfix?)

The fix must be used for each stwcx. Chip IBM Microelectronics. Mark Hatle wrote: > > David Gibson wrote: > > > > Ah, yes, I discovered ATOMIC_SYNC_FIX after I sent that, and have now > > turned it on. That should certainly fix the atomic ops, however there > > are quite a number of other place

support for only 255 processes on a 405

Dan Perhaps i dont understand. It looks like from the code that process id and pids dont match. Could you explain how this code works. Chip Dan Malek wrote: > > Ralph Blach wrote: > > > > Is there any support for having a special case for the 405 that would > > limit

support for only 255 processes on a 405

Is there any support for having a special case for the 405 that would limit the number of processes to 255. This means that the pid and context could be the same. This might be a performance gain. Chip ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

using the little endian bit 4xx mmu

Dan, Because its there, and its been hacked in here and the people here have found it VERY useful and convienent. 4xx specific or not, the people found it extremely convienent. Chip Dan Malek wrote: > > "Marti, Felix" wrote: > > > > I hacked it in a few hours: > > in arch/ppc/kernel/head_4xx.

using the little endian bit 4xx mmu

Is there any hope of getting an ioremap little endian in the 4xx code so the tlb would use little endian bit in the tlb? Thanks Chip ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

linuxppc.org

What has happened to linuxppc.org. I cant seem to get to it anymore. Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments

null console

for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010508/af7908c6/attachment.vcf

ppc little-endian port

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pte entries for the 440

? Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010424/decef62c/attachment.vcf

Walnut IDE support

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Speech Recognition Software

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ati 3D RAGE LT PRO on walnut 405

Has anybody gotten the ati 3d rage to work on a walnut 405? Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments

Why does the linux kernel?

. Thanks in advance. Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010402/f5045a0f/attachment.vcf

Whate kind of kernel errors cause an Segmentation Fault

What kind of kernel return codes will cause the C library to print out the message "Segmentation Fault" Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach U

booting HardHat on IBM 405GP

Does someone know how to determine the board's revision number? > -- next part ------ A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010327/4cc1192b/attachment.vcf

Proposed new kernel noncaching memory allocator for the 405gp

Dan, No, the transmit descriptors in the USB code are much less than a page. Look at ohci-usb.c Why do a kmalloc? And what about SCSI and it linked list? These need bytes and not whole pages. Any I'll do it and submitt it . Chip Dan Malek wrote: > Ralph Blach wrote: > &

Proposed new kernel noncaching memory allocator for the 405gp

Frank, Yes, but these allocate on a page boundry and I was thinking of something a little more granular. Any objections? Chip Frank Rowand wrote: > Ralph Blach wrote: > > > > > > > David Blythe wrote: > > > > I think something more general then pci_

Proposed new kernel noncaching memory allocator for the 405gp

functions that you say you have implemented? Chip Dan Malek wrote: > Ralph Blach wrote: > > > I propose a kmalloc_noncache and a kfree_noncached. > > > > These would be module and would be loaded when necessary. They would > > operate allocating say 16k (could be an

Proposed new kernel noncaching memory allocator for the 405gp

would carve out little chucks of it and the free routine would release it. It would also have a noncached to real routine to return the real address of a noncached section. Does this sound interesting? Chip David Blythe wrote: > Ralph Blach wrote: > > > > David, > >

Compiling/debugging 405GP and RISCWatch

Primagraphics Limited > New Cambridge House, Litlington, nr.Royston, Herts, SG8 0SS, UK > Tel. +44 1763 85, Fax. 853324, http://www.primagraphics.co.uk > -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 byt

es1371.o sound module on a IBM 405 walnut platform

Dan Malek wrote: > Ralph Blach wrote: > > > Well it does. And I recomend a new kernel interface, and Dan, I KNOW > > YOU WILL not like THE VERY IDEA, > > by here it is. > > > > > > By the same token, an interface to allocate noncached memory would be &g

es1371.o sound module on a IBM405 gp walnut

Brad, Well it was endian problems. I ran an mp3 to wav conversion that sox recomended. I then had to do a word swap on the 16 bit data and it sounded fine. Is there anyway to tell the driver that the samples are byte reversed? Chip Brad Parker wrote: > Ralph Blach wrote: > >Brad,

es1371.o sound module on a IBM405 gp walnut

I am trying to get an es1371. sound module working on an IBM405 walunt developement kit. 8 bit sound works ok but 16 bit sound sounds like noise. Will this driver have to be made Endian aware? Thanks in advance -- Ralph "Chip" Blach KF4WBK Chapel Hill, North Carolina ** Sent via the linuxpp

Going to sleep atomically

In a device driver, What is the best way to go to sleep atomically? Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded

ramdisk for initrd

it as init) > > hope you can use this > > bye > Andreas > -- > Life's not fair. But the root password helps ! :-) >http://schrecky.home.pages.de >Open minds. Open sources. Open future. > -- next part -

Wait queue question

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Wait queue question

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Big vs. Little endian was Re: Walnut user-space software problem

t; Also, I wanted to verify the size of the variable types in the > > > gcc compiler for the PowerPC. Please correct me if I'm > > > wrong. > > > > > > int - 32 bit signed integer > > > short - 16 bit signed integer > > > > correct for PPC. > > short always 16 > > long always 32 > > long long always 64 > > int = machine word size > > > > I hope I could point you in the proper direction, > > Rolf > > > -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010214/89faeac3/attachment.vcf

Patch for Soft-Float Problems w/ Glibc & Gcc?

value); > > return (status); > } > > pi.c: > > float > pi(void) > { > return (22.0/7.0); > } > > float_print.c: > > int float_print(const char *string, float value) > { > return (printf("%s: %f\n", string, val

WaitQueues.

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Multiple threads in a device driver

Can a device driver have multiple threads running it? If so, where are examples of this shown. Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail

New device Class

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new device class

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which errno should I use

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hdlc interface

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explantion of the tty driver

Is there a good explantion of the tty device driver in linux anywhere? Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded

8260 hdlc driver

Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20010122/45399da1/attachment.vcf

es1371 on the 405gp and Monta Vista Kernel

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pointers to ld.so.1

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How do I make a bigger ram disk

OK, How do I make a bigger ram disk image. I know this is a really basic question but I cant seem to find the instructions anywhere. Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach

Problems of the corss-compiler.

r include glibc for library. > > Please tell me what do you think about that And why the problem happen. > I'll wait your answers. > thank you. > -- next part ------ A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/2828/d08d61d7/attachment.vcf

es1371 driver just make noise

linux? If so, which one? Thanks Chip -- next part -- A non-text attachment was scrubbed... Name: rcblach.vcf Type: text/x-vcard Size: 247 bytes Desc: Card for Ralph Blach Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/2825/b8faf54d/attachment.vcf

es1371 sound cards

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error in assumptions in the handling of interrupts.

I would like explain a bug which I found in the 4xx interrupt controller code yesterday. In the ppc4xx_pic.c code their is a routine called ppcxxx_aic_disable_and_ack. The purpose of this code is disable interrupts on the level and reset the ISR. This will NOT work because for Level interrupts,

405gp pci mapping registers

The IBM405gp has 3 sets of PMM registers. These allow extreme flexibility in mapping the where and how the PCI memory is configured into processor memory. Each set of registers consist of 4 32 bit registers. register offset 0 is the local address register 4 is the mask/attribute

Enabling Video on the IBM PowerPC 405GP walnut system

Nikhil, I have video working on the Walnut board. By default, Open Bios leave the PMM's mapped in this manner. PMM0 maps all memory references from processor memory 0x8000 to PCI memory 0x8000. PMM1 maps all memory references from processor memory 0xA000 to PCI memory 0xA000. Th

Porting LinuxPPC

Daris, I disagree. I beleive that the Kernel load simply must be above 0x8000. And I you want to put a lot of memory in one of these systems, it had better be movable down from 0xc000. On the IBM405gp and I assume, the 8xx systems, all of real memory is pinned into a to TLB's. Well, if

Porting LinuxPPC

Daniel, Although I am not an expert, I really think the lowest kernel base is 0x8000. This is because the Linux which we have assumes that we have memory from 0x0 - 0x7fff avaliable for tasks. So I think the kernel will have to move above 0x8000. Chip Daniel Wu wrote: > > Hi, > >

Video Card with PowerPC initialization Code

Does anybody know of Video card which has a ROM that has PowerPC initializaiton in it? If so, what is it? Thanks Chip IBM MicroElectronics RTP, NC ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

ATI Xclaim 3D Plus(ATI Rage LT pro)

I am working in a port of linux on the PPC405gp and I would like to put in video support in. Does anybody have initialization code for the ATI Rage LT pro to initialize the card to 80x25 character mode? Thanks Chip IBM Microelectronics ** Sent via the linuxppc-embedded mail list. See http://li

405gc problem with shared libraries

I am attempting to run the latest 405gc port and am getting error. I boot up to sash, and then run the command ls everthing seems to run fine untill I get the message ./ls: error in loading shared libraries: libc.so.6: failed to map segment from shared object: Error 19 This message is from ld.

Data/instruction TLB miss handlers for the 405

Has anybody put in the Data/Instruction TLB miss handers for the 405 yet? Thanks Chip IBM MicroElectronics RTP, NC ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

using io remap in an init func

I am working on a port of linux to the IBM 405. I need to scan the PCI hardware and to do this I need a tlb entry for the indirect io addresses staring at 0xeec0. The function that sets up the indrect address is specified as an __init. If I use IOremap here to remap the address, will this t

mkevimg and mkirimg for little endian machines

Has anybody ported mkevimg and mkirimg to little endian machines? thanks chip ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/