Hi, Miroslav:
I am using calnex to test ptp. calnex can mimic the long path delay so it
is reasonable.
I am using switch chip, it has MAC timestamping and rx_delay, tx_delay are
compensated.
Thanks
Alex
Miroslav Lichvar 于2022年9月8日周四 21:26写道：
> On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton
On Thu, Sep 08, 2022 at 01:56:59PM +0200, Luigi 'Comio' Mantellini wrote:
> - How is the 1PPS driven? Is there any reclocking logic? You need to ask
> your FPGA-experts.
+1
The circuit the produces the 1 PPS could well delay the signal by ten
or more nanoseconds.
Thanks,
Richard
On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote:
> ptp4l[130171.662]: rms1 max2 freq-49 +/- 3 delay 9058 +/- 0
> my board has 1PPS output, I connect it to the master and compared with
> reference PPS.
> however, the 1pps time error is around 40 NS, which means my bo
Hi, Luigi:
I am really thankful for your nice suggestions.
1. The delay for pps cable to calnex is already compensated in calnex
configuration.
2. Yes, RX and TX path are asymmetry. the calnex can measure the T1, T4
and 2way time error, those time errors are only a few nano seconds, that
means cor
