Author: David Spickett
Date: 2023-09-06T08:48:19+01:00
New Revision: 6c3232b5150ffcca8d90ab364272323bb82655fb
URL:
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https://github.com/DavidSpickett updated
https://github.com/llvm/llvm-project/pull/65332:
>From 5b094742811697096f6e614eca28b0ca5729dc4c Mon Sep 17 00:00:00 2001
From: David Spickett
Date: Tue, 5 Sep 2023 15:04:05 +0100
Subject: [PATCH 1/3] [lldb][Docs] Add page about debugging lldb itself
We
@@ -0,0 +1,254 @@
+Debugging LLDB
DavidSpickett wrote:
I've renamed it just "Debugging". Assuming people read the first sentence it'll
be clear it's about debugging lldb itself.
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@@ -0,0 +1,254 @@
+Debugging LLDB
+==
+
+This page details various ways to debug LLDB itself and other LLDB tools. If
+you want to know how to use LLDB in general, please refer to
+:doc:`/use/tutorial`.
+
+As LLDB is generally split into 2 tools, ``lldb`` and ``lldb-se
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@@ -0,0 +1,254 @@
+Debugging LLDB
+==
+
+This page details various ways to debug LLDB itself and other LLDB tools. If
+you want to know how to use LLDB in general, please refer to
+:doc:`/use/tutorial`.
+
+As LLDB is generally split into 2 tools, ``lldb`` and ``lldb-se
@@ -0,0 +1,254 @@
+Debugging LLDB
+==
+
+This page details various ways to debug LLDB itself and other LLDB tools. If
+you want to know how to use LLDB in general, please refer to
+:doc:`/use/tutorial`.
+
+As LLDB is generally split into 2 tools, ``lldb`` and ``lldb-se
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@@ -0,0 +1,254 @@
+Debugging LLDB
+==
+
+This page details various ways to debug LLDB itself and other LLDB tools. If
+you want to know how to use LLDB in general, please refer to
+:doc:`/use/tutorial`.
+
+As LLDB is generally split into 2 tools, ``lldb`` and ``lldb-se
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DavidSpickett wrote:
There are some bits missing from this e.g. debugging packet exchanges but I
will hold that for another PR.
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https://github.com/HerrCai0907 updated
https://github.com/llvm/llvm-project/pull/65431:
>From 2b727285edb91a4a88add118745eabc08da9c6fd Mon Sep 17 00:00:00 2001
From: Congcong Cai
Date: Wed, 6 Sep 2023 09:55:20 +0800
Subject: [PATCH 1/2] [clang-tidy][misc-include-cleaner]Avoid fixes insert same
Author: Muhammad Omair Javaid
Date: 2023-09-06T14:03:21+05:00
New Revision: e82191469ec408a39cf13ebe6a7dfb03787f09c1
URL:
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DavidSpickett updated this revision to Diff 556016.
DavidSpickett added a comment.
Log when comp dir not found and carry on to fallback search.
Add a test for the search path being a symlink.
Repository:
rG LLVM Github Monorepo
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DavidSpickett marked 2 inline comments as done.
DavidSpickett added inline comments.
Comment at: lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp:1747-1754
if (!comp_dir) {
unit.SetDwoError(Status::createWithFormat(
"unable to locate relative .dwo d
DavidSpickett marked 2 inline comments as done.
DavidSpickett added inline comments.
Comment at: lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp:1779
+FileSystem::Instance().Resolve(dirspec);
+if (!FileSystem::Instance().IsDirectory(dirspec))
+ c
https://github.com/NuriAmari updated
https://github.com/llvm/llvm-project/pull/65179:
>From 5d395c85b84e5a554df4b092014d38123e666c6c Mon Sep 17 00:00:00 2001
From: Nuri Amari
Date: Tue, 29 Aug 2023 10:10:57 -0700
Subject: [PATCH 1/4] Add flags to dump IR to a file before and after LLVM
passes
@@ -0,0 +1,71 @@
+; RUN: mkdir -p %t/logs
+; RUN: rm -rf %t/logs
+
+; Basic dump before and after a single module pass
+; RUN: opt %s -disable-output -passes='no-op-module' -ir-dump-directory
%t/logs -dump-after=no-op-module -dump-before=no-op-module
+; RUN: find %t/logs -type f
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https://github.com/JDevlieghere approved this pull request.
Thanks for working on this!
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Author: David Spickett
Date: 2023-09-06T16:22:28+01:00
New Revision: ad2453a2db22cd5aefabb8961a0cf025f8f7eb03
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clayborg accepted this revision.
clayborg added a comment.
This revision is now accepted and ready to land.
Thanks a lot for acting on all feedback and getting all of the edge cases! LGTM
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ht
Author: Daniel Paoliello
Date: 2023-09-06T11:20:39-07:00
New Revision: a8138c3d2f2e5a64137a2aceb3094faf978786b9
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https://github.com/walter-erquinigo created
https://github.com/llvm/llvm-project/pull/65514:
We've been displaying types and addresses for containers, but that's not very
useful information. A better approach is to compose the summary of containers
with the summary of a few of its children.
N
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bulbazord added a comment.
This change seems mostly red in that we're removing a lot of things. What are
the replacements? I also see you're removing the API lock acquisition in a few
places, where does that now occur?
Comment at: lldb/bindings/python/python-wrapper.swig:266-
@@ -1,8 +1,9 @@
-from lldbsuite.test.lldbtest import *
import os
-import vscode
import time
+import vscode
River707 wrote:
Are the changes in this file necessary?
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@@ -132,6 +132,84 @@ std::vector GetStrings(const
llvm::json::Object *obj,
return strs;
}
+/// Create a short summary for a container that contains the summary of its
+/// first children, so that the user can get a glimpse of its contents at a
+/// glance.
+static std::opti
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@@ -132,6 +132,84 @@ std::vector GetStrings(const
llvm::json::Object *obj,
return strs;
}
+/// Create a short summary for a container that contains the summary of its
+/// first children, so that the user can get a glimpse of its contents at a
+/// glance.
+static std::opti
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>From e7ed33687a44992889df60eae5af03fb439aacc0 Mon Sep 17 00:00:00 2001
From: walter erquinigo
Date: Wed, 6 Sep 2023 10:38:41 -0400
Subject: [PATCH 1/2] [lldb-vscode] Display a more descriptive summary
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Author: Walter Erquinigo
Date: 2023-09-06T17:13:27-04:00
New Revision: 89a81ec2054919411eb8da1274557cbf97bbfe49
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None
>From 6529eb1ad2a4d5922c8a66d3a11514b5c406eac0 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Wed, 6 Sep 2023 17:15:56 -0400
Subject: [PATCH] [RISCV] Added definition of Ventana veyron-v1 processor.
--
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We were invoking GetChildAtIndex(0) without checking the number of children.
This was not crashing but was showing some warnings in python formatters.
>From 78d2b81b4a6fb55b98b42f6e3edd0f6d96f20fd8 Mon
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Author: Walter Erquinigo
Date: 2023-09-06T17:49:12-04:00
New Revision: 01c0a6a0a4c7f9101a35d2ab056191ecff117db5
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@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket
NuriAmari wrote:
I've tried this on a real application, and the output paths quickly get
extremely long. So long that we fail to create the directory structure. Perhaps
the nesting idea isn't the right choice after all.
https://github.com/llvm/llvm-project/pull/65179
__
https://github.com/silee2 created
https://github.com/llvm/llvm-project/pull/65539:
None
>From 863a72b4e099f4aa24e43fdaaeb2ab0e171a0381 Mon Sep 17 00:00:00 2001
From: "Lee, Sang Ik"
Date: Wed, 30 Aug 2023 13:44:02 -0700
Subject: [PATCH 01/13] Add SyclRuntimeWrappers and Add CMake option
MLIR_E
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Jianhui-Li wrote:
@rengolin @joker-eph @Hardcode84
FYI that this PR enables the current GPU dialect on Intel GPU as is, without
introducing stream/queue to the current GPU dialect.
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Hardcode84 wrote:
I suggest to extract `mgpu` interface changes and `serializetoSpirv` pass to 2
separate PRs.
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silee2 wrote:
> I suggest to extract `mgpu` interface changes and `serializetoSpirv` pass to
> 2 separate PRs.
Agree. And the changes are originally from different authors so should be
splitted.
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@@ -0,0 +1,70 @@
+//===- SerializeToSPIRV.cpp - Convert GPU kernel to SPIRV blob
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,70 @@
+//===- SerializeToSPIRV.cpp - Convert GPU kernel to SPIRV blob
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -811,8 +812,13 @@ LogicalResult
ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite(
// descriptor.
Type elementPtrType = this->getElementPtrType(memRefType);
auto stream = adaptor.getAsyncDependencies().front();
+
+ auto isHostShared = rewriter.create(
+ loc
https://github.com/joker-eph commented:
LGTM overall, this should likely get reviewed by @antiagainst / @kuhar ; and
it's be great if you can split the independent changes and send them ahead of
the e2e integration.
https://github.com/llvm/llvm-project/pull/65539
__
@@ -71,7 +71,8 @@ void GPUToSPIRVPass::runOnOperation() {
std::unique_ptr target =
spirv::getMemorySpaceToStorageClassTarget(*context);
spirv::MemorySpaceToStorageClassMap memorySpaceMap =
- spirv::mapMemorySpaceToVulkanStorageClass;
+ th
https://github.com/walter-erquinigo created
https://github.com/llvm/llvm-project/pull/65552:
Currently, if the user wants to inspect the raw version of a synthetic
variable, they have to go to the debug console and type `frame var ,
which is not a great experience. Taking inspiration from Code
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https://github.com/llvm/llvm-project/pull/65552
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https://github.com/River707 approved this pull request.
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Author: Walter Erquinigo
Date: 2023-09-06T20:13:48-04:00
New Revision: cf5d8def5cf66fbdfffa00a4845bd648ec58ed60
URL:
https://github.com/llvm/llvm-project/commit/cf5d8def5cf66fbdfffa00a4845bd648ec58ed60
DIFF:
https://github.com/llvm/llvm-project/commit/cf5d8def5cf66fbdfffa00a4845bd648ec58ed60.di
https://github.com/bulbazord review_requested
https://github.com/llvm/llvm-project/pull/6
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https://github.com/bulbazord created
https://github.com/llvm/llvm-project/pull/6:
lldb already has a `ValueSP` type. This was confusing to me when reading
TypeCategoryMap, especially when `ValueSP` is not qualified. From first glance
it looks like it's referring to a `std::shared_ptr` when
https://github.com/bulbazord review_requested
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https://github.com/silee2 edited https://github.com/llvm/llvm-project/pull/65539
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https://github.com/JDevlieghere approved this pull request.
I started looking at the diff before reading the description only to be
confused by the exact same thing.
https://github.com/llvm/llvm-project/pull/6
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lldb-c
https://github.com/keryell commented:
Quite interesting!
At some point it would be nice to have some design document or documentation
somewhere explaining how all these MLIR runners works, including this one.
Globally this PR add a SYCL runner, but it is very specific for Intel Level 0.
It would
@@ -116,6 +116,7 @@
add_definitions(-DMLIR_ROCM_CONVERSIONS_ENABLED=${MLIR_ENABLE_ROCM_CONVERSIONS})
set(MLIR_ENABLE_CUDA_RUNNER 0 CACHE BOOL "Enable building the mlir CUDA
runner")
set(MLIR_ENABLE_ROCM_RUNNER 0 CACHE BOOL "Enable building the mlir ROCm
runner")
+set(MLIR_E
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