https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/97824
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@@ -22,13 +22,13 @@ using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- if (std::optional> features =
+ if (const std::optional> features =
sys::getHostCPUFeatures(featu
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/97824
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@@ -15,22 +15,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include
+
using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- StringMap featu
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https://github.com/llvm/llvm-project/pull/97824
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https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/97824
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https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/90987
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/6] [AArch64] move extension information into tablgen
Gen
@@ -426,30 +532,40 @@ def FeatureSpecRestrict :
SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
def FeatureSB : Extension<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)" >;
+ "Enable v8.5
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/5] [AArch64] move extension information into tablgen
Gen
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/4] [AArch64] move extension information into tablgen
Gen
@@ -426,30 +532,40 @@ def FeatureSpecRestrict :
SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
def FeatureSB : Extension<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)" >;
+ "Enable v8.5
@@ -11,42 +11,123 @@
// A SubtargetFeature that can be toggled from the command line, and therefore
// has an AEK_* entry in ArmExtKind.
+//
+// If Function MultiVersioning (FMV) properties are left at their defaults
+// (FEAT_INIT, no dependencies, priority 0) it indiates tha
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/90320
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tmatheson-arm wrote:
Thanks for the comments everyone. Given that this requires an IR break and
additions to the importer, and there is still some question about which way to
go with the renaming (i.e. FEAT_ names or user-facing names) I think it makes
sense to defer renaming until later. For
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/3] [AArch64] move extension information into tablgen
Gen
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/3] [AArch64] move extension information into tablgen
Gen
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/90987
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/90320
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https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/90320
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
Author: Tomas Matheson
Date: 2022-11-09T11:52:35Z
New Revision: 103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
URL:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
DIFF:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94.diff
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