[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
https://github.com/mgudim created https://github.com/llvm/llvm-project/pull/65535: None >From 6529eb1ad2a4d5922c8a66d3a11514b5c406eac0 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH] [RISCV] Added definition of Ventana veyron-v1 processor. --

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
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[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
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[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread via lldb-commits
https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread Michael Maitland via lldb-commits
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[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-06 Thread Michael Maitland via lldb-commits
@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

2023-09-07 Thread via lldb-commits
@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket