[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

https://github.com/heiher approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/84716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/18.x: backport [C++20] [Moduls] Avoid computing odr hash for functions from comparing constraint expression (PR #84723)

llvmbot wrote: @llvm/pr-subscribers-clang-modules Author: Chuanqi Xu (ChuanqiXu9) Changes Backport 3f6bc1adf805681293c2ef0b93b708ff52244c00 This fixes a surprising regression introduced in https://github.com/llvm/llvm-project/issues/79240. Given we've backported that to 18.x. We need to

[llvm-branch-commits] [clang] release/18.x: backport [C++20] [Moduls] Avoid computing odr hash for functions from comparing constraint expression (PR #84723)

https://github.com/ChuanqiXu9 created https://github.com/llvm/llvm-project/pull/84723 Backport 3f6bc1adf805681293c2ef0b93b708ff52244c00 This fixes a surprising regression introduced in https://github.com/llvm/llvm-project/issues/79240. Given we've backported that to 18.x. We need to backport

[llvm-branch-commits] [clang] release/18.x: backport [C++20] [Moduls] Avoid computing odr hash for functions from comparing constraint expression (PR #84723)

https://github.com/ChuanqiXu9 milestoned https://github.com/llvm/llvm-project/pull/84723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [mlir] [mlir][IR][NFC] Make `replaceAllUsesWith` non-templatized (PR #84722)

llvmbot wrote: @llvm/pr-subscribers-mlir-core Author: Matthias Springer (matthias-springer) Changes Turn `RewriterBase::replaceAllUsesWith` into a non-templatized implementation, so that it can be made virtual and be overridden in the `ConversionPatternRewriter` in a subsequent change.

[llvm-branch-commits] [mlir] [mlir][IR][NFC] Make `replaceAllUsesWith` non-templatized (PR #84722)

https://github.com/matthias-springer created https://github.com/llvm/llvm-project/pull/84722 Turn `RewriterBase::replaceAllUsesWith` into a non-templatized implementation, so that it can be made virtual and be overridden in the `ConversionPatternRewriter` in a subsequent change. This change i

[llvm-branch-commits] [mlir] [mlir][IR] Trigger `notifyOperationReplaced` on `replaceAllOpUsesWith` (PR #84721)

llvmbot wrote: @llvm/pr-subscribers-mlir Author: Matthias Springer (matthias-springer) Changes Before this change: `notifyOperationReplaced` was triggered when calling `RewriteBase::replaceOp`. After this change: `notifyOperationReplaced` is triggered when `RewriterBase::replaceAllOpUses

[llvm-branch-commits] [mlir] [mlir][IR] Trigger `notifyOperationReplaced` on `replaceAllOpUsesWith` (PR #84721)

https://github.com/matthias-springer created https://github.com/llvm/llvm-project/pull/84721 Before this change: `notifyOperationReplaced` was triggered when calling `RewriteBase::replaceOp`. After this change: `notifyOperationReplaced` is triggered when `RewriterBase::replaceAllOpUsesWith` or

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -47,6 +48,15 @@ enum AtomicABI : unsigned { }; } // namespace RISCVAtomicAbiTag +namespace RISCVX3RegUse { +enum X3RegUsage : unsigned { + UNKNOWN = 0, + GP = 0, wangpc-pp wrote: Copy paste mistakes? Why all 0s? https://github.com/llvm/llvm-project/pull

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -24,6 +24,9 @@ .attribute priv_spec_revision, 0 # CHECK: attribute 12, 0 + wangpc-pp wrote: This blank should be added in Atomic ABI PR I think. https://github.com/llvm/llvm-project/pull/84598 ___ llvm-bran

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -520,3 +520,8 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; A6S: .attribute 14, 2 ; A6C: .attribute 14, 1 } + wangpc-pp wrote: No CHECKs for this test or I miss something here? https://github.com/llvm/llvm-project/pull/84598 ___

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

llvmbot wrote: @llvm/pr-subscribers-backend-loongarch Author: None (llvmbot) Changes Backport edd4c6c6dca4 Requested by: @SixWeining --- Full diff: https://github.com/llvm/llvm-project/pull/84716.diff 2 Files Affected: - (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

llvmbot wrote: @heiher What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/84716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinf

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/84716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

llvmbot wrote: @llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang Author: None (llvmbot) Changes Backport aeda1a6e800e 2f479b811274 Requested by: @SixWeining --- Full diff: https://github.com/llvm/llvm-project/pull/84715.diff 3 Files Affected: - (modified) clang/lib/Headers/l

[llvm-branch-commits] [llvm] release/18.x: [LoongArch] Make sure that the LoongArchISD::BSTRINS node uses the correct `MSB` value (#84454) (PR #84716)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84716 Backport edd4c6c6dca4 Requested by: @SixWeining >From 2eb997da54bab3fcc90ec2c60e76972bb75f5c7e Mon Sep 17 00:00:00 2001 From: wanglei Date: Mon, 11 Mar 2024 08:59:17 +0800 Subject: [PATCH] [LoongArch] Make sure

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

llvmbot wrote: @SixWeining What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/84715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/lis

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/84715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84715 Backport aeda1a6e800e 2f479b811274 Requested by: @SixWeining >From a31f312f41f39aa6894ebcb23837dc76b052f6ad Mon Sep 17 00:00:00 2001 From: wanglei Date: Tue, 5 Mar 2024 19:44:28 +0800 Subject: [PATCH 1/2] [Clan

[llvm-branch-commits] [llvm] c8a9929 - Revert "[llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984)"

Author: Lu Weining Date: 2024-03-11T10:31:16+08:00 New Revision: c8a99293cb41576acb1cdd6e90ff2a04059b0075 URL: https://github.com/llvm/llvm-project/commit/c8a99293cb41576acb1cdd6e90ff2a04059b0075 DIFF: https://github.com/llvm/llvm-project/commit/c8a99293cb41576acb1cdd6e90ff2a04059b0075.diff LO

[llvm-branch-commits] [llvm] release/18.x: [llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984) (PR #83540)

SixWeining wrote: > For the record, based on the principle of "explicit is better than implicit" > that generally holds, I'd favor an approach where such > compile-time-verifiable out-of-range operands are given compile-time errors, > or we should just pass through the value unmodified. Otherw

[llvm-branch-commits] [llvm] release/18.x: [llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984) (PR #83540)

https://github.com/SixWeining closed https://github.com/llvm/llvm-project/pull/83540 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

llvmbot wrote: @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) Changes Backport 862c7e0218f27b55a5b75ae59a4f73cd4610448d Requested by: @DianQK --- Full diff: https://github.com/llvm/llvm-project/pull/84698.diff 2 Files Affected: - (modified) llvm/lib/Target/X86/X86ISelLowering

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84698 Backport 862c7e0218f27b55a5b75ae59a4f73cd4610448d Requested by: @DianQK >From 4e1ce0cbafa9e2b4f7cb11249898a877deab48b4 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 10 Mar 2024 16:23:51 + Subject:

[llvm-branch-commits] [llvm] release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes (PR #84698)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/84698 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap &intAttr, }; } +static void mergeX3RegUse(DenseMap &intAttr, + const InputSectionBase *oldSection, + const InputSectionBase *newSection, + uns

[llvm-branch-commits] [openmp] release/18.x: [OpenMP] fix endianness dependent definitions in OMP headers for MSVC (#84540) (PR #84668)

https://github.com/xingxue-ibm approved this pull request. Yes, it will be great if this patch can be picked up by v18.x. The OpenMP runtime libomp won't build without the fix if the build compiler is MSVC. https://github.com/llvm/llvm-project/pull/84668