@@ -146,16 +127,12 @@ body: |
; CHECK-NEXT: $v7 = VMV1R_V $v12
; CHECK-NEXT: $v8 = VMV1R_V $v13
; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-;
@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
[RV32, RV64],
[RegInfo<32,32,32>, RegInfo<64,64,64>]>;
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+ bit IsVRegClass = 0;
+
@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
[RV32, RV64],
[RegInfo<32,32,32>, RegInfo<64,64,64>]>;
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+ bit IsVRegClass = 0;
+
brad0 wrote:
@topperc
https://github.com/llvm/llvm-project/pull/86424
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@@ -146,16 +127,12 @@ body: |
; CHECK-NEXT: $v7 = VMV1R_V $v12
; CHECK-NEXT: $v8 = VMV1R_V $v13
; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-;
@@ -146,16 +127,12 @@ body: |
; CHECK-NEXT: $v7 = VMV1R_V $v12
; CHECK-NEXT: $v8 = VMV1R_V $v13
; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-;
@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned
@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
[RV32, RV64],
[RegInfo<32,32,32>, RegInfo<64,64,64>]>;
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+ bit IsVRegClass = 0;
+
@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned
https://github.com/lukel97 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/84448
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@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned
https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/84448
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@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock ,
}
// VR->VR copies.
- if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
-return;
- }
-
- if
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/84894
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wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/84455
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wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/84448
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https://github.com/chenzheng1030 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/86375
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kiranchandramohan wrote:
I am away this week, will come back to this next week.
https://github.com/llvm/llvm-project/pull/85989
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llvmbot wrote:
@topperc @topperc What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/86424
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/86424
Backport 755b439694432d4f68e20e979b479cbc30602bb1
5d7fd6a04a6748936dece9d90481b2ba4ec97e53
Requested by: @brad0
>From 27130993eeca747b72e19ce500a38d6d8067362a Mon Sep 17 00:00:00 2001
From: yingopq
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/86424
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https://github.com/brad0 closed https://github.com/llvm/llvm-project/pull/84566
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