wlei-llvm wrote:
Measured `decode_pseudo_probe(llvm-profgen)` on a large binary with 1.7GB
`.pseudo_probe` section
Ported and used all the improvements in a whole.
Before those changes:
```
Time: 190s , RSS: 57.4GB
```
After those changes:
```
Time: 55s , RSS: 26.3GB
```
Awesome!
https://git
@@ -4,7 +4,7 @@
// RUN: %clangxx_asan -g -O0 -DSHARED_LIB -DSIZE=1 %s -fPIC -shared -o
%t-so-1.so
// RUN: %clangxx_asan -g -O0 -DSHARED_LIB -DSIZE=2 %s -fPIC -shared -o
%t-so-2.so
// RUN: %clangxx_asan -g -O0 %s %libdl -Wl,--export-dynamic -o %t
-// RUN: %env_asan_opts=report
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llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
Printing globals registration is internal debug
tracing and should be controlled with verbosity.
---
Full diff: https://github.com/llvm/llvm-project/pull/104404.diff
6 Files Affected:
-
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
They are quite noisy in used in test application.
---
Full diff: https://github.com/llvm/llvm-project/pull/104402.diff
1 Files Affected:
- (modified) compiler-rt/lib/asan/asan_poisoning.
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/104403.diff
1 Files Affected:
- (modified) compiler-rt/lib/sanitizer_common/sanitizer_common.h (+8-6)
``diff
diff --gi
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/104404
Printing globals registration is internal debug
tracing and should be controlled with verbosity.
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They are quite noisy in used in test application.
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farzonl wrote:
> > Your description and the bug you are adressing make sense. One point of
> > confusion I see now is our mapping of intrinsics to DXIL Ops. The
> > intrinsics still all use `LLVMType`. Is that going to be problem?
>
> I don't see why it would. LLVMType is perfectly reasonable
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
+
@@ -0,0 +1,63 @@
+; RUN: opt -S -dxil-op-lower %s | FileCheck %s
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+define void @test_bindings() {
+ ; RWBuffer Buf : register(u5, space3)
+ %typed0 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0)
+ @llvm.dx.
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bogner wrote:
> Your description and the bug you are adressing make sense. One point of
> confusion I see now is our mapping of intrinsics to DXIL Ops. The intrinsics
> still all use `LLVMType`. Is that going to be problem?
I don't see why it would. LLVMType is perfectly reasonable for describ
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/104247
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farzonl wrote:
Your description and the bug you are adressing make sense. One point of
confusion I see now is our mapping of intrinsics to DXIL Ops. The intrinsics
still all use `LLVMType`. Is that going to ba problem?
https://github.com/llvm/llvm-project/pull/104247
__
@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
--
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@@ -289,6 +289,43 @@ class OpLowerer {
});
}
+ void lowerTypedBufferStore(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int8Ty = IRB.getInt8Ty();
+Type *Int32Ty = IRB.getInt32Ty();
+
+replaceFunction(F, [&](CallInst *CI) -> Error {
--
@@ -23,7 +23,10 @@ MODULE_ANALYSIS("dxil-resource-md", DXILResourceMDAnalysis())
#ifndef MODULE_PASS
#define MODULE_PASS(NAME, CREATE_PASS)
#endif
+MODULE_PASS("dxil-intrinsic-expansion", DXILIntrinsicExpansion())
+MODULE_PASS("dxil-op-lower", DXILOpLowering())
+MODULE_PASS("dx
@@ -0,0 +1,63 @@
+; RUN: opt -S -dxil-op-lower %s | FileCheck %s
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+define void @test_bindings() {
+ ; RWBuffer Buf : register(u5, space3)
+ %typed0 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0)
+ @llvm.dx.
@@ -23,7 +23,10 @@ MODULE_ANALYSIS("dxil-resource-md", DXILResourceMDAnalysis())
#ifndef MODULE_PASS
#define MODULE_PASS(NAME, CREATE_PASS)
#endif
+MODULE_PASS("dxil-intrinsic-expansion", DXILIntrinsicExpansion())
+MODULE_PASS("dxil-op-lower", DXILOpLowering())
+MODULE_PASS("dx
https://github.com/s-barannikov requested changes to this pull request.
See https://github.com/llvm/llvm-project/pull/101662#issuecomment-2289589525
https://github.com/llvm/llvm-project/pull/101847
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@@ -0,0 +1,63 @@
+; RUN: opt -S -dxil-op-lower %s | FileCheck %s
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+define void @test_bindings() {
+ ; RWBuffer Buf : register(u5, space3)
+ %typed0 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0)
+ @llvm.dx.
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@@ -23,7 +23,10 @@ MODULE_ANALYSIS("dxil-resource-md", DXILResourceMDAnalysis())
#ifndef MODULE_PASS
#define MODULE_PASS(NAME, CREATE_PASS)
#endif
+MODULE_PASS("dxil-intrinsic-expansion", DXILIntrinsicExpansion())
+MODULE_PASS("dxil-op-lower", DXILOpLowering())
+MODULE_PASS("dx
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bogner wrote:
Depends on #104252
https://github.com/llvm/llvm-project/pull/104253
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Depends on #104251
https://github.com/llvm/llvm-project/pull/104252
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bogner wrote:
Depends on #104246, #104247, and #104248
https://github.com/llvm/llvm-project/pull/104251
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 3dd396dbdafff66dc208690b224cce1ecd0fc47a
8bc857ceae40b5c789df54f29a138db4532839aa --e
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Depends on #104248
https://github.com/llvm/llvm-project/pull/104250
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llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
The `@llvm.dx.typedBufferLoad` intrinsic is lowered to `@dx.op.bufferLoad`.
There's some complexity here due to translating from a vector return type to a
named struct and trying to avoid excessive I
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
The `@llvm.dx.typedBufferStore` intrinsic is lowered to `@dx.op.bufferStore`.
---
Full diff: https://github.com/llvm/llvm-project/pull/104253.diff
5 Files Affected:
- (modified) llvm/docs/Direct
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
The `@llvm.dx.handle.fromBinding` intrinsic is lowered either to the
`CreateHandle` op or a pair of `CreateHandleFromBinding` and `AnnotateHandle`
ops, depending on the DXIL version. Regardless of th
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
This wires up dxil-op-lower, dxil-intrinsic-expansion, dxil-translate-metadata,
and dxil-pretty-printer to the new pass manager, both as a matter of future
proofing the backend and so that they can b
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
@llvm/pr-subscribers-backend-spir-v
@llvm/pr-subscribers-hlsl
Author: Justin Bogner (bogner)
Changes
This updates the "dxil-metadata-emit" pass flag to be spelled
"dxil-translate-metadata" to better match the pass name.
---
Full diff: h
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
This introduces an anonymous class "OpLowerer" to help with lowering DXIL ops,
and moves the DXILOpBuilder there instead of creating a new one for every
operation. DXILOpBuilder is also changed to ow
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
LLVMType is both too broad and too narrow for defining DXIL operations, in
different ways. It's too broad in the sense that we don't need the full set of
MVTs - the set of types DXIL operations work
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104253
The `@llvm.dx.typedBufferStore` intrinsic is lowered to `@dx.op.bufferStore`.
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llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
DXIL operations that only have one signature behave one of two ways - either
they are always suffixed with a type like `dx.op.ThreadId.i32` and hence have
exactly one overload, or they're never suffi
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104252
The `@llvm.dx.typedBufferLoad` intrinsic is lowered to `@dx.op.bufferLoad`.
There's some complexity here due to translating from a vector return type to a
named struct and trying to avoid excessive IR coming out o
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
In 8cf85653b6f5 "[DirectX] Make DXILOpBuilder's API more useable" we introduced
specialized createOp methods for each DirectX op for convenience, but the API
is buggy and untested. It also isn't actu
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104251
The `@llvm.dx.handle.fromBinding` intrinsic is lowered either to the
`CreateHandle` op or a pair of `CreateHandleFromBinding` and `AnnotateHandle`
ops, depending on the DXIL version. Regardless of the DXIL version
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104250
This wires up dxil-op-lower, dxil-intrinsic-expansion, dxil-translate-metadata,
and dxil-pretty-printer to the new pass manager, both as a matter of future
proofing the backend and so that they can be used more fl
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104249
This updates the "dxil-metadata-emit" pass flag to be spelled
"dxil-translate-metadata" to better match the pass name.
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https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104248
This introduces an anonymous class "OpLowerer" to help with lowering DXIL ops,
and moves the DXILOpBuilder there instead of creating a new one for every
operation. DXILOpBuilder is also changed to own its IRBuilde
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104246
DXIL operations that only have one signature behave one of two ways - either
they are always suffixed with a type like `dx.op.ThreadId.i32` and hence have
exactly one overload, or they're never suffixed like `dx.o
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104247
LLVMType is both too broad and too narrow for defining DXIL operations, in
different ways. It's too broad in the sense that we don't need the full set of
MVTs - the set of types DXIL operations work on is much sma
https://github.com/bogner created
https://github.com/llvm/llvm-project/pull/104245
In 8cf85653b6f5 "[DirectX] Make DXILOpBuilder's API more useable" we introduced
specialized createOp methods for each DirectX op for convenience, but the API
is buggy and untested. It also isn't actually as useful
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/100699
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https://github.com/llvm/llvm-project/pull/100700
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Author: Valentin Clement (バレンタイン クレメン)
Date: 2024-08-14T13:44:34-07:00
New Revision: ec137c84529a30b16c051f6b633a7a7538bdc46c
URL:
https://github.com/llvm/llvm-project/commit/ec137c84529a30b16c051f6b633a7a7538bdc46c
DIFF:
https://github.com/llvm/llvm-project/commit/ec137c84529a30b16c051f6b633a7
llvmbot wrote:
@llvm/pr-subscribers-libcxx
Author: None (llvmbot)
Changes
Backport 4d08bb11eea5907fa9cdfe4c7bc9d5c91e79c6a7
Requested by: @ldionne
---
Full diff: https://github.com/llvm/llvm-project/pull/104117.diff
4 Files Affected:
- (modified) libcxx/include/complex (+6-3)
- (modi
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/104117
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/104117
Backport 4d08bb11eea5907fa9cdfe4c7bc9d5c91e79c6a7
Requested by: @ldionne
>From 983d8ddec66649977e90c61334d586e214dfd4e0 Mon Sep 17 00:00:00 2001
From: Louis Dionne
Date: Wed, 14 Aug 2024 14:04:22 -0400
Subject
Author: Florian Mayer
Date: 2024-08-14T10:54:34-07:00
New Revision: b968a0229074ad32accd7feef50f4f5394d7ac96
URL:
https://github.com/llvm/llvm-project/commit/b968a0229074ad32accd7feef50f4f5394d7ac96
DIFF:
https://github.com/llvm/llvm-project/commit/b968a0229074ad32accd7feef50f4f5394d7ac96.diff
vient wrote:
I think you need to merge it yourself? I don't have rights to do it.
https://github.com/llvm/llvm-project/pull/102924
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https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/102163
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https://github.com/llvm/llvm-project/pull/102163
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102884
>From 04fe70293a7fe2432eb55620c7fc5b05310c4f74 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 12 Aug 2024 15:26:25 +0400
Subject: [PATCH] AMDGPU/NewPM: Start filling out addIRPasses
This is not complet
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102867
>From bc07cf6778a51845d4b0947523bc3cb79b3a0f3f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 12 Aug 2024 13:09:55 +0400
Subject: [PATCH] AMDGPU/NewPM: Fill out passes in addCodeGenPrepare
AMDGPUAnnota
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102865
>From dc7ab092c8c9873c44a9f6b0d07bd0f30c288070 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 12 Aug 2024 12:46:00 +0400
Subject: [PATCH] AMDGPU: Declare pass control flags in header
This will allow th
jroelofs wrote:
https://github.com/llvm/llvm-project/issues/104055
https://github.com/llvm/llvm-project/pull/104027
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arsenm wrote:
### Merge activity
* **Aug 14, 12:49 PM EDT**: @arsenm started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/102815).
https://github.com/llvm/llvm-project/pull/102815
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efriedma-quic wrote:
Please also fix the comment before
AArch64TargetLowering::shouldExpandAtomicRMWInIR . (The comment is wrong; a
floating-point "exception" isn't an exception in the sense that it would cancel
an exclusive reservation.)
https://github.com/llvm/llvm-project/pull/103702
Author: ChiaHungDuan
Date: 2024-08-14T08:44:01-07:00
New Revision: af92207904334c8de7d3c483dc6c635abe2f228e
URL:
https://github.com/llvm/llvm-project/commit/af92207904334c8de7d3c483dc6c635abe2f228e
DIFF:
https://github.com/llvm/llvm-project/commit/af92207904334c8de7d3c483dc6c635abe2f228e.diff
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github-actions[bot] wrote:
This repository does not accept pull requests. Please follow
http://llvm.org/docs/Contributing.html#how-to-submit-a-patch for contribution
to LLVM.
https://github.com/llvm/llvm-project/pull/104042
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https://github.com/aaupov edited
https://github.com/llvm/llvm-project/pull/102789
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cor3ntin wrote:
Yes merging that is fine, it fixes a regression
https://github.com/llvm/llvm-project/pull/102924
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Christudasan Devadasan (cdevadas)
Changes
This definition shouldn't be in AMDGPU TM.
---
Full diff: https://github.com/llvm/llvm-project/pull/104038.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine
https://github.com/cdevadas ready_for_review
https://github.com/llvm/llvm-project/pull/104038
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cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/104038?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/104038
This definition shouldn't be in AMDGPU TM.
>From 6ab7119cd8b4e63dad2625b0aa9416e2898a3bbc Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Wed, 14 Aug 2024 20:50:30 +0530
Subject: [PATCH] [AMDGPU][R
@@ -0,0 +1,98 @@
+//===- SliceWalk.h - Helpers for performing IR slice walks ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-
@@ -363,9 +323,14 @@ static void createNewAliasScopesFromNoAliasParameter(
// Find the set of underlying pointers that this pointer is based on.
SmallPtrSet basedOnPointers;
- for (Value pointer : pointerArgs)
-llvm::copy(getUnderlyingObjectSet(pointer
@@ -0,0 +1,98 @@
+//===- SliceWalk.h - Helpers for performing IR slice walks ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-
https://github.com/gysit edited https://github.com/llvm/llvm-project/pull/103053
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https://github.com/gysit approved this pull request.
LGTM modulo nits!
https://github.com/llvm/llvm-project/pull/103053
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https://github.com/AaronBallman approved this pull request.
LGTM, but please add a release note when this lands.
https://github.com/llvm/llvm-project/pull/104027
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https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/103721
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https://github.com/cdevadas updated
https://github.com/llvm/llvm-project/pull/103721
>From a10910597e6ee30e87dd09a4f77fcfa1729873f0 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Wed, 14 Aug 2024 14:18:59 +0530
Subject: [PATCH 1/2] [AMDGPU][R600] Move R600TargetMachine into
R600Co
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/102789
>From ddcbb593f72ca47acaa82f9c14a7fd2c4e30903b Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Tue, 13 Aug 2024 03:51:31 -0700
Subject: [PATCH 1/2] Pass CurChildIndex by value
Created using spr 1.3.4
---
llvm/
https://github.com/bogner updated
https://github.com/llvm/llvm-project/pull/100699
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