Dinistro wrote:
As I'm not too familiar with these parts of MLIR, I'll not be able to review
this properly. Does someone else have capacity to do a pass on the logic of
this?
https://github.com/llvm/llvm-project/pull/101707
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https://github.com/Dinistro updated
https://github.com/llvm/llvm-project/pull/103053
>From a9fd34956d7a9ddfc06bcfaf011cec7e3c5ddcd2 Mon Sep 17 00:00:00 2001
From: Christian Ulmann
Date: Tue, 13 Aug 2024 12:46:30 +
Subject: [PATCH 1/6] MLIR, LLVM: Add an IR utility to perform proper slicing
https://github.com/Dinistro edited
https://github.com/llvm/llvm-project/pull/103053
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Dinistro wrote:
Please reduce this test to the absolute minimum that still tests your change.
The IR does not need to compute anything useful, but the test should fail when
you would revert only your C++ changes.
Additionally, try to reduce the `CHECK`s to a
Dinistro wrote:
> The final `OneShotConversionPatternRewriter` will support everything that
> `ConversionPatternRewriter` supports. A few helper functions are still
> missing in this PR:
>
> * `applySignatureConversion`
> * `convertRegionTypes`
> * `convertNonEntryRegionTypes`
> * `replaceUses
https://github.com/Dinistro commented:
IIUC, this inherits from `ConversionPatternRewriter` to ensure that the
conversion patterns can be used with the new
`OneShotConversionPatternRewriter`. While this makes sense from a functional
perspective, the introduced inheritance relation seems a bit
https://github.com/Dinistro created
https://github.com/llvm/llvm-project/pull/91464
This commit modifies Mem2Reg's API to always attempt a full promotion on all
the passed in "allocators". This ensures that the pass does not require
unnecessary walks over the regions and improves caching benef
https://github.com/Dinistro updated
https://github.com/llvm/llvm-project/pull/85813
>From 2a1b83dae932b23d7160e0b29f6d3b0ff173bb46 Mon Sep 17 00:00:00 2001
From: Christian Ulmann
Date: Tue, 19 Mar 2024 15:33:34 +
Subject: [PATCH 1/2] [MLIR][LLVM][SROA] Support incorrectly typed memory
acce
@@ -384,16 +468,17 @@ bool LLVM::GEPOp::canRewire(const
DestructurableMemorySlot &slot,
// dynamic indices can never be properly rewired.
if (!getDynamicIndices().empty())
return false;
+ TODO: This is not necessary, I think.
+ // if (slot.elemType != getElemTyp
https://github.com/Dinistro created
https://github.com/llvm/llvm-project/pull/85813
This commit relaxes the assumption of type consistency for LLVM dialect load
and store operations in SROA. Instead, there is now a check that loads and
stores are in the bounds specified by the sub-slot they ac
https://github.com/Dinistro approved this pull request.
https://github.com/llvm/llvm-project/pull/84955
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Dinistro wrote:
Here we have to wait for the build bots, as they are mandatory.
https://github.com/llvm/llvm-project/pull/79603
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https://github.com/Dinistro updated
https://github.com/llvm/llvm-project/pull/77093
>From 33ee6deadd6318adcfc45dba1d39bc38514bcd4b Mon Sep 17 00:00:00 2001
From: Christian Ulmann
Date: Fri, 5 Jan 2024 13:20:10 +
Subject: [PATCH 1/2] [MLIR][LLVM] Add distinct identifier to the DISubprogram
https://github.com/Dinistro created
https://github.com/llvm/llvm-project/pull/77093
This commit adds an optional distinct attribute parameter to the
DISubprogramAttr. This enables modeling of distinct subprograms, as required
for LLVM IR. This change is required to avoid accidential uniquing o
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