[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

dc03-work wrote: > > > > Submit your PRs to `main` branch > > > > > > > > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I > > > think it's OK. > > > > > > No, your target branch is wrong. Either you should want to merge into > > `main` or into a branch for another PR

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

dc03-work wrote: > > Submit your PRs to `main` branch > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I think > it's OK. No, your target branch is wrong. Either you should want to merge into `main` or into a branch for another PR created by `spr`. However, in this case

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

dc03-work wrote: Manually landed this PR in https://github.com/llvm/llvm-project/commit/208a9850e6a4b64ad6311361735d27a9c6cbd8ec, because I still don't understand how stacking on GitHub works... https://github.com/llvm/llvm-project/pull/85042 ___ llv

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/dc03-work edited https://github.com/llvm/llvm-project/pull/85042 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/dc03-work closed https://github.com/llvm/llvm-project/pull/85042 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

dc03-work wrote: > It looks like this comes from the lowerIfMemSizeNotByteSizePow2. Custom is > often best avoided unless there is not anther way, or the change is quite > target-dependant. > > Can we try something like this instead? > > ``` > .clampMaxNumElements(0, s8, 16) > .cl

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/dc03-work updated https://github.com/llvm/llvm-project/pull/85042 >From ec953a06c9a3c9a29155bc07dfc3a1bdb033ee23 Mon Sep 17 00:00:00 2001 From: Dhruv Chawla Date: Wed, 13 Mar 2024 10:36:35 +0530 Subject: [PATCH] [AArch64][GlobalISel] Avoid splitting loads of large vector typ

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

dc03-work wrote: This PR is actually stacked on https://github.com/llvm/llvm-project/pull/85038. Sorry for the noise earlier. https://github.com/llvm/llvm-project/pull/85042 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85039)

dc03-work wrote: Okay... I give up on trying to fix this through spr... I'll create my stacks manually next time 😞 https://github.com/llvm/llvm-project/pull/85039 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.l

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85039)

https://github.com/dc03-work closed https://github.com/llvm/llvm-project/pull/85039 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85042)

https://github.com/dc03-work created https://github.com/llvm/llvm-project/pull/85042 This patch adds custom legalization for G_LOAD where it splits loads of fixed-width vector types larger than 128 bits into loads of 128-bit vectors with the same element type. This is an improvement to what w

[llvm-branch-commits] [llvm] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85039)

https://github.com/dc03-work edited https://github.com/llvm/llvm-project/pull/85039 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85039)

dc03-work wrote: This patch is meant to be stacked on https://github.com/llvm/llvm-project/pull/85038. It looks like spr did something weird here... https://github.com/llvm/llvm-project/pull/85039 ___ llvm-branch-commits mailing list llvm-branch-comm

[llvm-branch-commits] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85039)

https://github.com/dc03-work created https://github.com/llvm/llvm-project/pull/85039 This patch adds custom legalization for G_LOAD where it splits loads of fixed-width vector types larger than 128 bits into loads of 128-bit vectors with the same element type. This is an improvement to what was

[llvm-branch-commits] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85037)

https://github.com/dc03-work closed https://github.com/llvm/llvm-project/pull/85037 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Avoid splitting loads of large vector types into individual element loads (PR #85037)

dc03-work wrote: Looks like I messed up with spr... https://github.com/llvm/llvm-project/pull/85037 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

dc03-work wrote: Merged with #81830 in #82740 https://github.com/llvm/llvm-project/pull/81831 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

https://github.com/dc03-work closed https://github.com/llvm/llvm-project/pull/81831 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {s16, v8s16}, {s32, v2s32}, {s32, v4s32}}) + .moreElementsIf( dc03-work wrote: As I noted in my commit messag

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

dc03-work wrote: This PR is stacked on top of https://github.com/llvm/llvm-project/pull/81830. Sorry for the long branch names on both, I do not know how to change the default branch names with SPR https://github.com/llvm/llvm-project/pull/81831 ___

[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

https://github.com/dc03-work created https://github.com/llvm/llvm-project/pull/81831 i8 vectors do not have their sizes changed as I noticed regressions in some tests when that was done. ___ llvm-branch-commits mailing list llvm-branch-commits@lists