arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158272?utm_source=stack-comment-downstack-mergeability-warning";
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158273?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158274
Replace the target uses of PointerLikeRegClass with RegClassByHwMode
>From cbdfe4d18061f72bb5b3ba5577f9a8bd40fb210c Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PA
https://github.com/arsenm ready_for_review
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158240?utm_source=stack-comment-downstack-mergeability-warning";
@@ -1296,6 +1303,157 @@ struct AAAMDGPUNoAGPR
const char AAAMDGPUNoAGPR::ID = 0;
+/// An abstract attribute to propagate the function attribute
+/// "amdgpu-cluster-dims" from kernel entry functions to device functions.
+struct AAAMDGPUClusterDims
+: public StateWrapper {
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158246?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158224?utm_source=stack-comment-downstack-mergeability-warning";
@@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
// will pick deprecated instructions.
def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
+//===--===//
+// HwMo
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158278?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/158278
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None
>From f1396376f57e2ce24cabbdf5324a9f14e3bf837c Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH] Mips: Switch to RegClassByHwMode
---
.../Target/Mips/AsmP
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/158271?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> LGTM with the clang-format fix
I'm specifically ignoring that one since it's reformatting the entire large
function
https://github.com/llvm/llvm-project/pull/158240
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@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158246
>From e5032294b4979c4b7f2367cee30c24d42901714b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 17:27:37 +0900
Subject: [PATCH 1/2] AMDGPU: Move spill pseudo special case out of
adjustAllocata
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158225
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.
>From 808f13e18dc34dba52fa06b8e6281e06dbbcac45 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: F
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/158224
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/146075
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@@ -1296,6 +1303,157 @@ struct AAAMDGPUNoAGPR
const char AAAMDGPUNoAGPR::ID = 0;
+/// An abstract attribute to propagate the function attribute
+/// "amdgpu-cluster-dims" from kernel entry functions to device functions.
+struct AAAMDGPUClusterDims
+: public StateWrapper {
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157409
None
>From ac19605eb9b39362c28433d1cada25f50dbe2ebb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 8 Sep 2025 18:41:41 +0900
Subject: [PATCH] PPC: Use StringRef for subtarget constructor arguments
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/157206
>From 0d4d26ae9d6ee802c46d8115ccee28a9470aaced Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 08:50:20 +0900
Subject: [PATCH] PPC: Split 64bit target feature into 64bit and 64bit-support
Thi
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/157206
>From 0d4d26ae9d6ee802c46d8115ccee28a9470aaced Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 08:50:20 +0900
Subject: [PATCH] PPC: Split 64bit target feature into 64bit and 64bit-support
Thi
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157409?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157400?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/157400
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157054?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156655
>From 61b4ecaf9130602ed184ed505be6ed76d7e13f2e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 20:08:48 +0900
Subject: [PATCH] AMDGPU: Fix definitions of DS ret atomics with AGPRs
These are 2
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156890?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/157216
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157216?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157216
The AV operand classes should be used directly at the top level
of the load/store definitions. Inline the remaining use into the
strange MUBUF TFE vs. non-TFE usecase, which needed a special case
for 16-bit operan
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/157215
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157215
Avoid using getLdStRegisterOperand hidden at the bottom
of the class hierarchy.
>From a72a09db9aa9a037860dab5a50a7ec39629439ee Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 15:31:08 +0900
S
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157206
This was being used for 2 different purposes.
The TargetMachine constructor prepends +64bit based on isPPC64
triples as a mode switch. The same feature name was also explicitly
added to different processors, maki
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157206?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157054
None
>From 6992c2aa84c17fb2d965fe014efa7cb794ba643c Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 15:09:34 +0900
Subject: [PATCH] AMDGPU: Remove tablegen bz30254 workarounds from BUF
instr
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/157054
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/157037
AMDGPU: Fix using unaligned vgprs in mimg error test
These instructions really have 2 errors, from the unsupported
image base instruction plus the unaligned vgpr usage. This
test intends to test the base instruct
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/157037?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From c7238cff2feb2f7e1e7d7b0f55ae5b9917a682a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From a09ada3d217bcf5728f32d7a16c334fb0330e617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
Th
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156880
This should be a low level function used to interpret an
MCInstrDesc that only depends on the hwmode. It should not depend
on other dynamic context like the parent function. In general more
ABI properties like thi
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156890
Incremental step towards removing the special case hack
in TargetInstrInfo::getRegClass.
>From c0b9ff92d356aca252e8dc2e82f5e31be676316b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 13:08:0
@@ -1,381 +1,633 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-atomic-optimizer-strategy=None
< %s | FileCheck
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156880?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From c7238cff2feb2f7e1e7d7b0f55ae5b9917a682a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 22f1911b5b5f7a25d5d9cb74feb864341ef9a782 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156655
>From 61b4ecaf9130602ed184ed505be6ed76d7e13f2e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 20:08:48 +0900
Subject: [PATCH] AMDGPU: Fix definitions of DS ret atomics with AGPRs
These are 2
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From a09ada3d217bcf5728f32d7a16c334fb0330e617 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
Th
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156695
>From 25ff1b6a8940230deaa680241f9ce67d7896ab5d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 22:33:01 +0900
Subject: [PATCH] AMDGPU: Define agpr versions of ds permute instructions
Correctl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156696
>From 1b6877bd4a0ef4a30fcd0728b6e1864200969bc8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 4 Sep 2025 00:00:22 +0900
Subject: [PATCH] AMDGPU: Remove the DS special case in getRegClass
These instruct
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
arsenm wrote:
No. This needs new support in AMDGPURewriteAGPRCopyMFMA (which will also need a
renaming...)
https://github.com/llvm/llvm-proje
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156655?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156655
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156655
These are 2-data operations that need to use all-AGPR or all-VGPR
inputs. Stop defining them with AVLdSt data operands, and add _agpr
variants.
>From 90b88ef0d60e4d01cdd3864a8a8e30a8b5a6744d Mon Sep 17 00:00:00 2
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156580
>From 7ffe987d382e0e5d5cf7b1bc26000e0d997facf0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 10:58:25 +0900
Subject: [PATCH] AMDGPU: Change DS classes to use RegisterOperand parameters
Star
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From 1d1c4cd57f52e437487f668148d4945f8af9db36 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
Th
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156581
>From 1d1c4cd57f52e437487f668148d4945f8af9db36 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 12:06:53 +0900
Subject: [PATCH] AMDGPU: Change FLAT classes to use RegisterOperand parameters
Th
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/156580
>From 7ffe987d382e0e5d5cf7b1bc26000e0d997facf0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 3 Sep 2025 10:58:25 +0900
Subject: [PATCH] AMDGPU: Change DS classes to use RegisterOperand parameters
Star
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155560
>From 493b50264a7f348de647e9817fbd2dcbff81b95a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:17:00 +0900
Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc
This a
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156406?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/156405
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arsenm wrote:
Seems #156419 is sufficient to fix the issue
https://github.com/llvm/llvm-project/pull/156406
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 20442f6adbd765db0493edabef85228b56b0a1ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155603
>From 5c284f46a1063d5d0788c25a0d37ba019c171d54 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 16:19:23 +0900
Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in
usesConstan
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156402
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to mat
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153025
>From e9015799806374bc266257627df96ae2c2dfd43e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:05:44 +0900
Subject: [PATCH] AMDGPU: Add test for mfma rewrite pass respecting optnone
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153026
>From 46f04e8aefd98d782131616030857eb51dc8b1fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:12:49 +0900
Subject: [PATCH 1/2] AMDGPU: Add tests for every mfma intrinsic v-to-a mapping
M
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153025
>From e9015799806374bc266257627df96ae2c2dfd43e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:05:44 +0900
Subject: [PATCH] AMDGPU: Add test for mfma rewrite pass respecting optnone
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153026
>From 46f04e8aefd98d782131616030857eb51dc8b1fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 11 Aug 2025 19:12:49 +0900
Subject: [PATCH 1/2] AMDGPU: Add tests for every mfma intrinsic v-to-a mapping
M
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From 8961a0c7eb2c5fc7f93ad2d79e8dd2b6b3eab03a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156406
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 96904665ffd481eab0087e1a7c2edcc6ef0bb915 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156420
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155595
>From a6e2e0d83c2724f04313372df0deda5d1f889ed6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 19:39:38 +0900
Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on
incomplete
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/156580
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156580
Start stripping out the uses of getLdStRegisterOperand. This
added a confusing level of indirection where the class at the
definition point was not the actual class used. This was also
pulling in the AV class usag
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156580?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156581?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/156581
This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevan
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155595
>From a6e2e0d83c2724f04313372df0deda5d1f889ed6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 19:39:38 +0900
Subject: [PATCH 1/2] AMDGPU: Fix DPP combiner using isOperandLegal on
incomplete
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155603
>From a5a742a691fba41cf607a0ce20382a20d8719777 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 16:19:23 +0900
Subject: [PATCH 1/2] AMDGPU: Fix fixme for out of bounds indexing in
usesConstan
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155607
>From 20442f6adbd765db0493edabef85228b56b0a1ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From 05821956deebe21b8dd2bdd0a5962a0987d42775 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155615
>From 05821956deebe21b8dd2bdd0a5962a0987d42775 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 26 Aug 2025 23:53:57 +0900
Subject: [PATCH] AMDGPU: Fold 64-bit immediate into copy to AV class
This is in
https://github.com/arsenm closed
https://github.com/llvm/llvm-project/pull/156406
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https://github.com/arsenm updated
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>From 96904665ffd481eab0087e1a7c2edcc6ef0bb915 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:35:53 +0900
Subject: [PATCH] AMDGPU: Refactor isImmOperandLegal
The goal is to expose more v
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155560
>From f1272175f9c0f695e7c3182ddebd0a1fa03b5cc0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:17:00 +0900
Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc
This a
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/155560
>From f1272175f9c0f695e7c3182ddebd0a1fa03b5cc0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 27 Aug 2025 15:17:00 +0900
Subject: [PATCH] AMDGPU: Add version of isImmOperandLegal for MCInstrDesc
This a
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