https://github.com/mbrkusanin created
https://github.com/llvm/llvm-project/pull/171166
Use new scoped enums with type set to uint8_t.
From 46da7be139d82c2271688faaa5cb8364be91f930 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin
Date: Mon, 8 Dec 2025 18:05:45 +0100
Subject: [PATCH] [AMDGPU] Use
https://github.com/mbrkusanin updated
https://github.com/llvm/llvm-project/pull/170904
From 882c6ec5c217e4a29963ba735a7068b28d92bf96 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin
Date: Fri, 5 Dec 2025 19:21:27 +0100
Subject: [PATCH 1/2] [AMDGPU] Use different name scope for MIMGBaseOpcode
Def
https://github.com/mbrkusanin created
https://github.com/llvm/llvm-project/pull/170904
Define MIMGBaseOpcode values with `enum class` instead of regular
`enum` so they will be in a separate name scope from regular
opcodes. These two groups of opcodes should not be mixed and
keeping them in diffe
https://github.com/mbrkusanin approved this pull request.
https://github.com/llvm/llvm-project/pull/168411
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@@ -1509,18 +1509,18 @@ multiclass MIMG_Gather
: MIMG_Gather;
-class MIMG_IntersectRay_Helper {
- int num_addrs = !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11));
+class MIMG_IntersectRay_Helper {
+ int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16,
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
