[llvm-branch-commits] [llvm] 65d5327 - [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.

2022-03-02 Thread Shao-Ce SUN via llvm-branch-commits
Author: Shao-Ce SUN Date: 2022-03-03T14:52:36+08:00 New Revision: 65d53279b1fddeae4bd455d588ea7527aed50bb9 URL: https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9 DIFF: https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9.diff L

[llvm-branch-commits] [llvm] 967296b - [RISCV] Fix inline asm errors in zfinx

2022-03-01 Thread Shao-Ce SUN via llvm-branch-commits
Author: Shao-Ce SUN Date: 2022-03-02T14:31:23+08:00 New Revision: 967296bfefee9740b1dfb4644970d776e1b37b5b URL: https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b DIFF: https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b.diff L

[llvm-branch-commits] [llvm] 192d968 - [RISCV] add the MC layer support of Zfinx extension

2022-02-17 Thread Shao-Ce SUN via llvm-branch-commits
Author: Shao-Ce SUN Date: 2022-02-18T00:12:38+08:00 New Revision: 192d9680c1b11877e84b7431626ac8321c52d9c1 URL: https://github.com/llvm/llvm-project/commit/192d9680c1b11877e84b7431626ac8321c52d9c1 DIFF: https://github.com/llvm/llvm-project/commit/192d9680c1b11877e84b7431626ac8321c52d9c1.diff L