Author: Craig Topper Date: 2020-11-23T14:17:06-08:00 New Revision: 03dab46d7f7323ba2b37416829cc364a4de4f294
URL: https://github.com/llvm/llvm-project/commit/03dab46d7f7323ba2b37416829cc364a4de4f294 DIFF: https://github.com/llvm/llvm-project/commit/03dab46d7f7323ba2b37416829cc364a4de4f294.diff LOG: [RISCV] Remove unused VM register class Nothing references this class today so it looks like some leftover. Differential Revision: https://reviews.llvm.org/D91977 Added: Modified: llvm/lib/Target/RISCV/RISCVRegisterInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index cda75c816ed1..6d6babce98ca 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -331,13 +331,6 @@ def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64, def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>; -def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add - (sequence "V%u", 25, 31), - (sequence "V%u", 8, 24), - (sequence "V%u", 0, 7))> { - let Size = 64; -} - def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> { let Size = 64; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits