Author: Craig Topper Date: 2021-01-08T11:36:31-08:00 New Revision: 0875a9da2a387ce8e6aa28db9db933d605c3e6cc
URL: https://github.com/llvm/llvm-project/commit/0875a9da2a387ce8e6aa28db9db933d605c3e6cc DIFF: https://github.com/llvm/llvm-project/commit/0875a9da2a387ce8e6aa28db9db933d605c3e6cc.diff LOG: [RISCV] Cleanup a few section comments in RISCVInstrInfoVPseudos.td. NFC Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 2557b49f0c1c..ac179619db61 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2389,7 +2389,7 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> { } //===----------------------------------------------------------------------===// -// Pseudo instructions and patterns. +// Pseudo instructions //===----------------------------------------------------------------------===// let Predicates = [HasStdExtV] in { @@ -2459,10 +2459,6 @@ foreach eew = EEWList in { defm PseudoVLE # eew # FF : VPseudoUSLoad; } -//===----------------------------------------------------------------------===// -// Pseudo Instructions -//===----------------------------------------------------------------------===// - //===----------------------------------------------------------------------===// // 12. Vector Integer Arithmetic Instructions //===----------------------------------------------------------------------===// @@ -2587,7 +2583,7 @@ defm PseudoVWMACCSU : VPseudoTernaryW_VV_VX; defm PseudoVWMACCUS : VPseudoTernaryW_VX</*IsFloat*/false>; //===----------------------------------------------------------------------===// -// 12.15. Vector Integer Merge Instructions +// 12.16. Vector Integer Merge Instructions //===----------------------------------------------------------------------===// defm PseudoVMERGE : VPseudoBinaryV_VM_XM_IM; @@ -3222,7 +3218,7 @@ defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenabl defm "" : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>; //===----------------------------------------------------------------------===// -// 12.15. Vector Integer Merge Instructions +// 12.16. Vector Integer Merge Instructions //===----------------------------------------------------------------------===// defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits