Author: Lucas Prates Date: 2020-12-18T11:11:56Z New Revision: 51fe17b0471a2b0a27ce038426e6b996218061a2
URL: https://github.com/llvm/llvm-project/commit/51fe17b0471a2b0a27ce038426e6b996218061a2 DIFF: https://github.com/llvm/llvm-project/commit/51fe17b0471a2b0a27ce038426e6b996218061a2.diff LOG: [AArch64] Add support for the SPE-EEF feature This is an addition to the existing Statistical Profiling extension, which introduces an extra system register that is enabled by the new 'spe-eef' subtarget feature. Patch written by Simon Tatham. Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D92391 Added: llvm/test/MC/AArch64/spe.s Modified: llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/AArch64/AArch64SystemOperands.td Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 6457c86e926f..2df4e92e42cb 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -415,6 +415,9 @@ def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", "true", "Enable Branch Record Buffer Extension">; +def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", + "true", "Enable extra register in the Statistical Profiling Extension">; + def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", "true", "Enable fine grained virtualization traps extension">; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 5c55dd9834a7..c1d8fd1aba3d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -159,6 +159,8 @@ def HasLS64 : Predicate<"Subtarget->hasLS64()">, AssemblerPredicate<(all_of FeatureLS64), "ls64">; def HasBRBE : Predicate<"Subtarget->hasBRBE()">, AssemblerPredicate<(all_of FeatureBRBE), "brbe">; +def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">, + AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 169e8494f173..641450a6d776 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -185,6 +185,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { bool HasETE = false; bool HasTRBE = false; bool HasBRBE = false; + bool HasSPE_EEF = false; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove = false; diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index a753b4d4fbc4..a69aa68405d4 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1593,6 +1593,10 @@ foreach n = 0-31 in { } } +// Statistical Profiling Extension system register +let Requires = [{ {AArch64::FeatureSPE_EEF} }] in +def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>; + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcAppleA7} }] in diff --git a/llvm/test/MC/AArch64/spe.s b/llvm/test/MC/AArch64/spe.s new file mode 100644 index 000000000000..a6fb46291dea --- /dev/null +++ b/llvm/test/MC/AArch64/spe.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s + +msr PMSNEVFR_EL1, x0 +mrs x1, PMSNEVFR_EL1 +// CHECK: msr PMSNEVFR_EL1, x0 // encoding: [0x20,0x99,0x18,0xd5] +// CHECK: mrs x1, PMSNEVFR_EL1 // encoding: [0x21,0x99,0x38,0xd5] _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits