Author: Hsiangkai Wang Date: 2020-12-11T14:02:56+08:00 New Revision: 5aa584ec713c6aefc34ecc997d98c5f05210fa07
URL: https://github.com/llvm/llvm-project/commit/5aa584ec713c6aefc34ecc997d98c5f05210fa07 DIFF: https://github.com/llvm/llvm-project/commit/5aa584ec713c6aefc34ecc997d98c5f05210fa07.diff LOG: [RISCV] Separate masked and unmasked definitions for pseudo instructions. Differential Revision: https://reviews.llvm.org/D93012 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/lib/Target/RISCV/RISCVMCInstLower.cpp llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index a0bcea883118..32762fd2803e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -126,36 +126,88 @@ def RISCVVPseudosTable : GenericTable { // Helpers to define the diff erent pseudo instructions. //===----------------------------------------------------------------------===// -multiclass pseudo_binary<VReg result_reg_class, - VReg op1_reg_class, - DAGOperand op2_kind, - LMULInfo vlmul > { - let Constraints = "$rd = $merge", - Uses = [VL, VTYPE], VLIndex = 5, SEWIndex = 6, MergeOpIndex = 1, - BaseInstr = !cast<Instruction>(!subst("Pseudo", "", NAME)) in - def "_"# vlmul.MX : Pseudo<(outs result_reg_class:$rd), - (ins result_reg_class:$merge, - op1_reg_class:$rs2, op2_kind:$rs1, - VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), - []>, - RISCVVPseudo; +class PseudoToVInst<string PseudoInst> { + string VInst = !subst("_M8", "", + !subst("_M4", "", + !subst("_M2", "", + !subst("_M1", "", + !subst("_MF2", "", + !subst("_MF4", "", + !subst("_MF8", "", + !subst("_MASK", "", + !subst("Pseudo", "", PseudoInst))))))))); } -multiclass pseudo_binary_v_vv_vx_vi<Operand imm_type = simm5, - bit force_earlyclobber = 0> { +class VPseudoBinary<VReg RetClass, + VReg Op1Class, + DAGOperand Op2Class> : + Pseudo<(outs RetClass:$rd), + (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew), []>, + RISCVVPseudo { + let Uses = [VL, VTYPE]; + let VLIndex = 3; + let SEWIndex = 4; + let MergeOpIndex = -1; + let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); +} + +class VPseudoBinaryMask<VReg RetClass, + VReg Op1Class, + DAGOperand Op2Class> : + Pseudo<(outs RetClass:$rd), + (ins RetClass:$merge, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>, + RISCVVPseudo { + let Constraints = "$rd = $merge"; + let Uses = [VL, VTYPE]; + let VLIndex = 5; + let SEWIndex = 6; + let MergeOpIndex = 1; + let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); +} + +multiclass VPseudoBinary<VReg RetClass, + VReg Op1Class, + DAGOperand Op2Class, + LMULInfo MInfo> { + def "_" # MInfo.MX : VPseudoBinary<RetClass, Op1Class, Op2Class>; + def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class>; +} + +multiclass VPseudoBinaryV_VV { let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in foreach m = MxList.m in { let VLMul = m.value in - { - defvar evr = m.vrclass; - defm _VV : pseudo_binary<evr, evr, evr, m>; - defm _VX : pseudo_binary<evr, evr, GPR, m>; - defm _VI : pseudo_binary<evr, evr, imm_type, m>; - } + defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>; + } +} + +multiclass VPseudoBinaryV_VX { + let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in + foreach m = MxList.m in + { + let VLMul = m.value in + defm _VX : VPseudoBinary<m.vrclass, m.vrclass, GPR, m>; + } +} + +multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> { + let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in + foreach m = MxList.m in + { + let VLMul = m.value in + defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>; } } +multiclass VPseudoBinary_VV_VX_VI<Operand ImmType = simm5> { + defm "" : VPseudoBinaryV_VV; + defm "" : VPseudoBinaryV_VX; + defm "" : VPseudoBinaryV_VI<ImmType>; +} + //===----------------------------------------------------------------------===// // Helpers to define the diff erent patterns. //===----------------------------------------------------------------------===// @@ -167,7 +219,7 @@ multiclass pat_vop_binary<SDNode vop, ValueType mask_type, int sew, LMULInfo vlmul, - VReg result_reg_class, + VReg RetClass, VReg op_reg_class, bit swap = 0> { @@ -175,10 +227,8 @@ multiclass pat_vop_binary<SDNode vop, def : Pat<(result_type (vop (op_type op_reg_class:$rs1), (op_type op_reg_class:$rs2))), - (instruction (result_type (IMPLICIT_DEF)), - op_reg_class:$rs1, + (instruction op_reg_class:$rs1, op_reg_class:$rs2, - (mask_type zero_reg), VLMax, sew)>; } @@ -300,7 +350,7 @@ foreach vti = AllVectors in //===----------------------------------------------------------------------===// // Pseudo instructions. -defm PseudoVADD : pseudo_binary_v_vv_vx_vi; +defm PseudoVADD : VPseudoBinary_VV_VX_VI; // Whole-register vector patterns. defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>; diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp index 876d557ec79d..b1aacfe878b9 100644 --- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp +++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp @@ -176,6 +176,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, } OutMI.addOperand(MCOp); } + + // Unmasked pseudo instructions define MergeOpIndex to -1. + // Append dummy mask operand to V instructions. + if (RVV->getMergeOpIndex() == -1) + OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); + return true; } diff --git a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir index b2b07343be2f..16e2aefc61ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir +++ b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir @@ -31,8 +31,7 @@ body: | %4:vr = PseudoVLE64_V_M1 %5, %1, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) %7:vr = IMPLICIT_DEF %6:vr = PseudoVLE64_V_M1 %7, %2, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) - %9:vr = IMPLICIT_DEF - %8:vr = PseudoVADD_VV_M1 %9, killed %4, killed %6, $noreg, %3, 64, implicit $vl, implicit $vtype + %8:vr = PseudoVADD_VV_M1 killed %4, killed %6, %3, 64, implicit $vl, implicit $vtype PseudoVSE64_V_M1 killed %8, %0, $noreg, %3, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) PseudoRET @@ -40,16 +39,15 @@ body: | # POST-INSERTER: %0:gpr = COPY $x13 # POST-INSERTER: %4:vr = IMPLICIT_DEF -# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype # POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %4, %2, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) # POST-INSERTER: %6:vr = IMPLICIT_DEF -# POST-INSERTER: dead %11:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype # POST-INSERTER: %7:vr = PseudoVLE64_V_M1 %6, %1, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -# POST-INSERTER: %8:vr = IMPLICIT_DEF +# POST-INSERTER: dead %11:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, $noreg, -1, implicit $vl, implicit $vtype # POST-INSERTER: dead %12:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype -# POST-INSERTER: %9:vr = PseudoVADD_VV_M1 %8, killed %5, killed %7, $noreg, $noreg, -1, implicit $vl, implicit $vtype -# POST-INSERTER: dead %13:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype -# POST-INSERTER: PseudoVSE64_V_M1 killed %9, %3, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) +# POST-INSERTER: PseudoVSE64_V_M1 killed %8, %3, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) # CODEGEN: vsetvli a4, a3, e64,m1,ta,mu # CODEGEN-NEXT: vle64.v v25, (a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll index d88d354f6302..b8093f5008e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll @@ -24,18 +24,16 @@ define void @vadd_vint64m1( ; PRE-INSERTER: %3:vr = PseudoVLE64_V_M1 %4, %1, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) ; PRE-INSERTER: %6:vr = IMPLICIT_DEF ; PRE-INSERTER: %5:vr = PseudoVLE64_V_M1 %6, %2, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -; PRE-INSERTER: %8:vr = IMPLICIT_DEF -; PRE-INSERTER: %7:vr = PseudoVADD_VV_M1 %8, killed %3, killed %5, $noreg, $x0, 64, implicit $vl, implicit $vtype +; PRE-INSERTER: %7:vr = PseudoVADD_VV_M1 killed %3, killed %5, $x0, 64, implicit $vl, implicit $vtype ; PRE-INSERTER: PseudoVSE64_V_M1 killed %7, %0, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) ; POST-INSERTER: %4:vr = IMPLICIT_DEF -; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %4, %1, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) ; POST-INSERTER: %6:vr = IMPLICIT_DEF -; POST-INSERTER: dead %10:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %6, %2, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -; POST-INSERTER: %8:vr = IMPLICIT_DEF +; POST-INSERTER: dead %10:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: %7:vr = PseudoVADD_VV_M1 killed %3, killed %5, $noreg, -1, implicit $vl, implicit $vtype ; POST-INSERTER: dead %11:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype -; POST-INSERTER: %7:vr = PseudoVADD_VV_M1 %8, killed %3, killed %5, $noreg, $noreg, -1, implicit $vl, implicit $vtype -; POST-INSERTER: dead %12:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: PseudoVSE64_V_M1 killed %7, %0, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits