Author: Jay Foad Date: 2020-12-01T10:15:32Z New Revision: 839c9635edce4f6ed348b154a4e755ff8263d366
URL: https://github.com/llvm/llvm-project/commit/839c9635edce4f6ed348b154a4e755ff8263d366 DIFF: https://github.com/llvm/llvm-project/commit/839c9635edce4f6ed348b154a4e755ff8263d366.diff LOG: [AMDGPU] Simplify some generation checks. NFC. Added: Modified: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index b8b747ea8f99..d1e5fe59e910 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -4866,7 +4866,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, case AMDGPU::SRC_PRIVATE_BASE: case AMDGPU::SRC_PRIVATE_LIMIT: case AMDGPU::SRC_POPS_EXITING_WAVE_ID: - return !isCI() && !isSI() && !isVI(); + return isGFX9Plus(); case AMDGPU::TBA: case AMDGPU::TBA_LO: case AMDGPU::TBA_HI: @@ -4877,7 +4877,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, case AMDGPU::XNACK_MASK: case AMDGPU::XNACK_MASK_LO: case AMDGPU::XNACK_MASK_HI: - return !isCI() && !isSI() && !isGFX10Plus() && hasXNACK(); + return (isVI() || isGFX9()) && hasXNACK(); case AMDGPU::SGPR_NULL: return isGFX10Plus(); default: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits