Author: Matt Arsenault Date: 2021-01-07T13:13:25-05:00 New Revision: c9122ddef5213fbdd2d82c473a74e1742010f62f
URL: https://github.com/llvm/llvm-project/commit/c9122ddef5213fbdd2d82c473a74e1742010f62f DIFF: https://github.com/llvm/llvm-project/commit/c9122ddef5213fbdd2d82c473a74e1742010f62f.diff LOG: CodeGen: Refactor regallocator command line and target selection Make the sequence of passes to select and rewrite instructions to physical registers be a target callback. This is to prepare to allow targets to split register allocation into multiple phases. Added: Modified: llvm/include/llvm/CodeGen/TargetPassConfig.h llvm/lib/CodeGen/TargetPassConfig.cpp llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp Removed: ################################################################################ diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index 0cbb758a7ee8..b4787710379f 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -460,10 +460,10 @@ class TargetPassConfig : public ImmutablePass { /// regalloc pass. virtual FunctionPass *createRegAllocPass(bool Optimized); - /// Add core register alloator passes which do the actual register assignment + /// Add core register allocator passes which do the actual register assignment /// and rewriting. \returns true if any passes were added. - virtual bool addRegAssignmentFast(); - virtual bool addRegAssignmentOptimized(); + virtual bool addRegAssignAndRewriteFast(); + virtual bool addRegAssignAndRewriteOptimized(); }; void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 41d96b9e6016..e844d03854e2 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -1308,7 +1308,7 @@ FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { return createTargetRegisterAllocator(Optimized); } -bool TargetPassConfig::addRegAssignmentFast() { +bool TargetPassConfig::addRegAssignAndRewriteFast() { if (RegAlloc != &useDefaultRegisterAllocator && RegAlloc != &createFastRegisterAllocator) report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc."); @@ -1317,7 +1317,7 @@ bool TargetPassConfig::addRegAssignmentFast() { return true; } -bool TargetPassConfig::addRegAssignmentOptimized() { +bool TargetPassConfig::addRegAssignAndRewriteOptimized() { // Add the selected register allocation pass. addPass(createRegAllocPass(true)); @@ -1327,12 +1327,6 @@ bool TargetPassConfig::addRegAssignmentOptimized() { // Finally rewrite virtual registers. addPass(&VirtRegRewriterID); - // Perform stack slot coloring and post-ra machine LICM. - // - // FIXME: Re-enable coloring with register when it's capable of adding - // kill markers. - addPass(&StackSlotColoringID); - return true; } @@ -1348,7 +1342,7 @@ void TargetPassConfig::addFastRegAlloc() { addPass(&PHIEliminationID, false); addPass(&TwoAddressInstructionPassID, false); - addRegAssignmentFast(); + addRegAssignAndRewriteFast(); } /// Add standard target-independent passes that are tightly coupled with @@ -1391,7 +1385,13 @@ void TargetPassConfig::addOptimizedRegAlloc() { // PreRA instruction scheduling. addPass(&MachineSchedulerID); - if (addRegAssignmentOptimized()) { + if (addRegAssignAndRewriteOptimized()) { + // Perform stack slot coloring and post-ra machine LICM. + // + // FIXME: Re-enable coloring with register when it's capable of adding + // kill markers. + addPass(&StackSlotColoringID); + // Allow targets to expand pseudo instructions depending on the choice of // registers before MachineCopyPropagation. addPostRewrite(); diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 85709eb731e2..21da566b639f 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -170,11 +170,11 @@ class NVPTXPassConfig : public TargetPassConfig { void addFastRegAlloc() override; void addOptimizedRegAlloc() override; - bool addRegAssignmentFast() override { + bool addRegAssignAndRewriteFast() override { llvm_unreachable("should not be used"); } - bool addRegAssignmentOptimized() override { + bool addRegAssignAndRewriteOptimized() override { llvm_unreachable("should not be used"); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 71e8e1485b75..af16d799d1dc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -326,10 +326,10 @@ class WebAssemblyPassConfig final : public TargetPassConfig { void addPreEmitPass() override; // No reg alloc - bool addRegAssignmentFast() override { return false; } + bool addRegAssignAndRewriteFast() override { return false; } // No reg alloc - bool addRegAssignmentOptimized() override { return false; } + bool addRegAssignAndRewriteOptimized() override { return false; } }; } // end anonymous namespace _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
