Author: Craig Topper Date: 2020-11-27T11:37:25-08:00 New Revision: f325b4bbceb5e680e64532dd018b3c0a36d1b01a
URL: https://github.com/llvm/llvm-project/commit/f325b4bbceb5e680e64532dd018b3c0a36d1b01a DIFF: https://github.com/llvm/llvm-project/commit/f325b4bbceb5e680e64532dd018b3c0a36d1b01a.diff LOG: [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of their PatFrags can match. NFCI We had an zexti32 after a sign_extend_inreg. The AND X, 0xffffffff part of the zexti32 should never occur since SimplifyDemandedBits from the sign_extend_inreg would have removed it. We also had sexti32 as the root node of a pattern, but SelectionDAGISel matches assertsext early before the tablegen based patterns are evaluated. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoD.td llvm/lib/Target/RISCV/RISCVInstrInfoF.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index 6c36f53cd563..3aaae2de9d8b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -368,7 +368,7 @@ def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>; // because fpto[u|s]i produce poison if the value can't fit into the target. // We match the single case below because fcvt.wu.d sign-extends its result so // is cheaper than fcvt.lu.d+sext.w. -def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32), +def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32), (FCVT_WU_D $rs1, 0b001)>; // [u]int32->fp diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 79281e7d8a5b..5162b5ca4291 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -400,7 +400,7 @@ def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; let Predicates = [HasStdExtF, IsRV64] in { def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; -def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)), +def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32), (FMV_X_W FPR32:$src)>; // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits