Author: Paul C. Anagnostopoulos Date: 2021-01-01T10:21:02-05:00 New Revision: f4c39ccd2214800958d9dbd44d023d63f9891cba
URL: https://github.com/llvm/llvm-project/commit/f4c39ccd2214800958d9dbd44d023d63f9891cba DIFF: https://github.com/llvm/llvm-project/commit/f4c39ccd2214800958d9dbd44d023d63f9891cba.diff LOG: [TableGen] Continue cleaning up .td files This pass includes LLVM and MLIR files. Differential Revision: https://reviews.llvm.org/D93864 Added: Modified: llvm/include/llvm/IR/IntrinsicsARM.td llvm/include/llvm/IR/IntrinsicsNVVM.td llvm/include/llvm/Option/OptParser.td llvm/lib/Target/NVPTX/NVPTXIntrinsics.td mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td mlir/include/mlir/IR/OpBase.td Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index edc84a54ccc2..0eb27cc34462 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -922,7 +922,7 @@ multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params, list<IntrinsicProperty> props = [IntrNoMem]> { def "": Intrinsic<rets, params, props>; def _predicated: Intrinsic<rets, params # [pred, - !if(!eq(!cast<string>(rets[0]), "llvm_anyvector_ty"), + !if(!eq(rets[0], llvm_anyvector_ty), LLVMMatchType<0>, rets[0])], props>; } diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td index 37a9aceaa61e..2ab48cfc4bb7 100644 --- a/llvm/include/llvm/IR/IntrinsicsNVVM.td +++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td @@ -231,11 +231,11 @@ class NVVM_MMA_OPS<int _ = 0> { def NVVM_MMA_OPS : NVVM_MMA_OPS; -// Returns [1] if this combination of layout/satf is supported, [] otherwise. +// Returns true if this combination of layout/satf is supported; false otherwise. // MMA ops must provide all parameters. Loads and stores -- only frags and layout_a. // The class is used to prevent generation of records for the unsupported variants. // E.g. -// foreach _ = NVVM_MMA_SUPPORTED<...>.ret in = +// if NVVM_MMA_SUPPORTED<...>.ret then // def : FOO<>; // The record will only be defined for supported ops. // class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b="-", int satf=-1> { @@ -261,20 +261,20 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b # !if(!eq(!size(frags), 4), frags[2].ptx_elt_type # frags[3].ptx_elt_type, "?"); - list<int> ret = !cond( + bit ret = !cond( // Sub-int MMA only supports fixed A/B layout. // b1 does not support .satf. - !eq(mma#":"#satf, "b1:row:col:0") : [1], + !eq(mma#":"#satf, "b1:row:col:0") : true, // mma.m8n8k4 has no .satf modifier. !and(!eq(frags[0].geom, "m8n8k4"), - !ne(satf, 0)): [], + !ne(satf, 0)): false, // mma.m8n8k4 has no C=f32 D=f16 variant. - !eq(gcd, "m8n8k4:f32f16"): [], - !eq(mma, "s4:row:col") : [1], - !eq(mma, "u4:row:col") : [1], - !eq(mma, "s4:row:col") : [1], - !eq(mma, "u4:row:col") : [1], + !eq(gcd, "m8n8k4:f32f16"): false, + !eq(mma, "s4:row:col") : true, + !eq(mma, "u4:row:col") : true, + !eq(mma, "s4:row:col") : true, + !eq(mma, "u4:row:col") : true, // Sub-int load/stores have fixed layout for A and B. !and(!eq(layout_b, "-"), // It's a Load or Store op !or(!eq(ld, "b1:a:row"), @@ -288,13 +288,13 @@ class NVVM_MMA_SUPPORTED<list<WMMA_REGS> frags, string layout_a, string layout_b !eq(ld, "u4:a:row"), !eq(ld, "u4:b:col"), !eq(ldf, "u4:c"), - !eq(ldf, "u4:d"))) : [1], + !eq(ldf, "u4:d"))) : true, // All other sub-int ops are not supported. - !eq(t, "b1") : [], - !eq(t, "s4") : [], - !eq(t, "u4") : [], + !eq(t, "b1") : false, + !eq(t, "s4") : false, + !eq(t, "u4") : false, // All other (non sub-int) are OK. - true: [1] + true: true ); } @@ -4120,11 +4120,11 @@ class NVVM_WMMA_ST<WMMA_REGS Frag, string Layout, int WithStride> foreach layout = ["row", "col"] in { foreach stride = [0, 1] in { foreach frag = NVVM_MMA_OPS.all_ld_ops in - foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in + if NVVM_MMA_SUPPORTED<[frag], layout>.ret then def WMMA_NAME_LDST<"load", frag, layout, stride>.record : NVVM_WMMA_LD<frag, layout, stride>; foreach frag = NVVM_MMA_OPS.all_st_ops in - foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in + if NVVM_MMA_SUPPORTED<[frag], layout>.ret then def WMMA_NAME_LDST<"store", frag, layout, stride>.record : NVVM_WMMA_ST<frag, layout, stride>; } @@ -4143,7 +4143,7 @@ foreach layout_a = ["row", "col"] in { foreach layout_b = ["row", "col"] in { foreach satf = [0, 1] in { foreach op = NVVM_MMA_OPS.all_mma_ops in { - foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in { + if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then { def WMMA_NAME_MMA<layout_a, layout_b, satf, op[0], op[1], op[2], op[3]>.record : NVVM_WMMA_MMA<layout_a, layout_b, satf, diff --git a/llvm/include/llvm/Option/OptParser.td b/llvm/include/llvm/Option/OptParser.td index e96e54131569..c1233297a7e6 100644 --- a/llvm/include/llvm/Option/OptParser.td +++ b/llvm/include/llvm/Option/OptParser.td @@ -146,7 +146,7 @@ class ValuesCode<code valuecode> { code ValuesCode = valuecode; } class ImpliedByAnyOf<list<Option> options, code value = "true"> { code ImpliedCheck = !foldl("false", options, accumulator, option, - !strconcat(accumulator, " || ", !cast<string>(option.KeyPath))); + !strconcat(accumulator, " || ", option.KeyPath)); code ImpliedValue = value; } diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index b3c8a219c97d..8ccd47c0fcfd 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -7523,10 +7523,10 @@ defset list<WMMA_INSTR> MMA_LDSTs = { foreach space = [".global", ".shared", ""] in { foreach addr = [imem, Int32Regs, Int64Regs, MEMri, MEMri64] in { foreach frag = NVVM_MMA_OPS.all_ld_ops in - foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in + if NVVM_MMA_SUPPORTED<[frag], layout>.ret then def : WMMA_LOAD<WMMA_REGINFO<frag>, layout, space, stride, addr>; foreach frag = NVVM_MMA_OPS.all_st_ops in - foreach _ = NVVM_MMA_SUPPORTED<[frag], layout>.ret in + if NVVM_MMA_SUPPORTED<[frag], layout>.ret then def : WMMA_STORE_D<WMMA_REGINFO<frag>, layout, space, stride, addr>; } // addr } // space @@ -7584,7 +7584,7 @@ defset list<WMMA_INSTR> MMAs = { foreach layout_b = ["row", "col"] in { foreach satf = [0, 1] in { foreach op = NVVM_MMA_OPS.all_mma_ops in { - foreach _ = NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret in { + if NVVM_MMA_SUPPORTED<op, layout_a, layout_b, satf>.ret then { def : WMMA_MMA<WMMA_REGINFO<op[0]>, WMMA_REGINFO<op[1]>, WMMA_REGINFO<op[2]>, diff --git a/mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td b/mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td index b18da2358243..02feed751e03 100644 --- a/mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td +++ b/mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td @@ -113,7 +113,7 @@ class IsScalableVectorOfLengthPred<list<int> allowedLengths> : class ScalableVectorOfLength<list<int> allowedLengths> : Type< IsScalableVectorOfLengthPred<allowedLengths>, - " of length " # StrJoinInt<allowedLengths, "/">.result>; + " of length " # !interleave(allowedLengths, "/")>; class ScalableVectorOfLengthAndType<list<int> allowedLengths, list<Type> allowedTypes> : Type< diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td index 124adb789cb3..ef5efc9c8281 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td @@ -258,10 +258,10 @@ class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName, llvm::Function *fn = llvm::Intrinsic::getDeclaration( module, llvm::Intrinsic::}] # enumName # [{, - { }] # StrJoin<!listconcat( + { }] # !interleave(!listconcat( ListIntSubst<resultPattern, overloadedResults>.lst, ListIntSubst<LLVM_IntrPatterns.operand, - overloadedOperands>.lst)>.result # [{ + overloadedOperands>.lst), ", ") # [{ }); auto operands = lookupValues(opInst.getOperands()); }] # !if(!gt(numResults, 0), "$res = ", "") @@ -326,7 +326,8 @@ class LLVM_VectorReductionAcc<string mnem> llvm::Function *fn = llvm::Intrinsic::getDeclaration( module, llvm::Intrinsic::vector_reduce_}] # mnem # [{, - { }] # StrJoin<ListIntSubst<LLVM_IntrPatterns.operand, [1]>.lst>.result # [{ + { }] # !interleave(ListIntSubst<LLVM_IntrPatterns.operand, [1]>.lst, + ", ") # [{ }); auto operands = lookupValues(opInst.getOperands()); llvm::FastMathFlags origFM = builder.getFastMathFlags(); diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td index 9e32af59f397..2ed11015b960 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td @@ -176,8 +176,8 @@ class Extension<list<StrEnumAttrCase> extensions> : Availability { // Pack all extensions as a static array and get its reference. let instancePreparation = !if(!empty(extensions), "", "static const ::mlir::spirv::Extension exts[] = {" # - StrJoin<!foreach(ext, extensions, - "::mlir::spirv::Extension::" # ext.symbol)>.result # + !interleave(!foreach(ext, extensions, + "::mlir::spirv::Extension::" # ext.symbol), ", ") # "}; " # // The following manual ArrayRef constructor call is to satisfy GCC 5. "ArrayRef<::mlir::spirv::Extension> " # @@ -217,8 +217,8 @@ class Capability<list<I32EnumAttrCase> capabilities> : Availability { // Pack all capabilities as a static array and get its reference. let instancePreparation = !if(!empty(capabilities), "", "static const ::mlir::spirv::Capability caps[] = {" # - StrJoin<!foreach(cap, capabilities, - "::mlir::spirv::Capability::" # cap.symbol)>.result # + !interleave(!foreach(cap, capabilities, + "::mlir::spirv::Capability::" # cap.symbol), ", ") # "}; " # // The following manual ArrayRef constructor call is to satisfy GCC 5. "ArrayRef<::mlir::spirv::Capability> " # @@ -3025,7 +3025,7 @@ class IOrUI<int width> class SignlessOrUnsignedIntOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, IOrUI<w>), - StrJoinInt<widths, "/">.result # "-bit signless/unsigned integer">; + !interleave(widths, "/") # "-bit signless/unsigned integer">; def SPV_IsArrayType : CPred<"$_self.isa<::mlir::spirv::ArrayType>()">; def SPV_IsCooperativeMatrixType : diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td index 0ceef0ce70a4..609b4109dc5e 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td @@ -29,8 +29,8 @@ class Tosa_QuantizedType<string n, list<int> params, bit signed> ".getStorageTypeIntegralWidth() == " # !head(params)>]>, "Q" # !if (signed, "int", "uint") # !head(params) # " type"> { string name = n; - string asTraitArgsStr = - StrJoinInt<params>.result # !if(signed, ", true", ", false"); + string asTraitArgsStr = !interleave(params, ", ") # + !if(signed, ", true", ", false"); } //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td index dfea9fed70a5..12460b4e16b6 100644 --- a/mlir/include/mlir/IR/OpBase.td +++ b/mlir/include/mlir/IR/OpBase.td @@ -38,16 +38,6 @@ class StrFunc<string r> { string result = r; } -// TODO: Use !interleave() directly rather than through StrJoin/StrJoinInt. - -// Concatenates a list of strings with a separator (default ", ") -class StrJoin<list<string> strings, string sep = ", "> : - StrFunc<!interleave(strings, sep)>; - -// Concatenates a list of integers into a string with a separator (default ", ") -class StrJoinInt<list<int> integers, string sep = ", "> : - StrFunc<!interleave(integers, sep)>; - //===----------------------------------------------------------------------===// // Predicate definitions //===----------------------------------------------------------------------===// @@ -354,7 +344,7 @@ class AnyTypeOf<list<Type> allowedTypes, string description = "", // Satisfy any of the allowed type's condition Or<!foreach(allowedtype, allowedTypes, allowedtype.predicate)>, !if(!eq(description, ""), - StrJoin<!foreach(t, allowedTypes, t.description), " or ">.result, + !interleave(!foreach(t, allowedTypes, t.description), " or "), description)>; // Integer types. @@ -371,7 +361,7 @@ class AnyI<int width> class AnyIntOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, AnyI<w>), - StrJoinInt<widths, "/">.result # "-bit integer", + !interleave(widths, "/") # "-bit integer", "::mlir::IntegerType">; def AnyI1 : AnyI<1>; @@ -395,7 +385,7 @@ class I<int width> class SignlessIntOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, I<w>), - StrJoinInt<widths, "/">.result # "-bit signless integer">; + !interleave(widths, "/") # "-bit signless integer">; def I1 : I<1>; def I8 : I<8>; @@ -418,7 +408,7 @@ class SI<int width> class SignedIntOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, SI<w>), - StrJoinInt<widths, "/">.result # "-bit signed integer">; + !interleave(widths, "/") # "-bit signed integer">; def SI1 : SI<1>; def SI8 : SI<8>; @@ -441,7 +431,7 @@ class UI<int width> class UnsignedIntOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, UI<w>), - StrJoinInt<widths, "/">.result # "-bit unsigned integer">; + !interleave(widths, "/") # "-bit unsigned integer">; def UI1 : UI<1>; def UI8 : UI<8>; @@ -470,7 +460,7 @@ class F<int width> class FloatOfWidths<list<int> widths> : AnyTypeOf<!foreach(w, widths, F<w>), - StrJoinInt<widths, "/">.result # "-bit float">; + !interleave(widths, "/") # "-bit float">; def F16 : F<16>; def F32 : F<32>; @@ -560,7 +550,7 @@ class IsVectorOfRankPred<list<int> allowedRanks> : // Any vector where the rank is from the given `allowedRanks` list class VectorOfRank<list<int> allowedRanks> : Type< IsVectorOfRankPred<allowedRanks>, - " of ranks " # StrJoinInt<allowedRanks, "/">.result, "::mlir::VectorType">; + " of ranks " # !interleave(allowedRanks, "/"), "::mlir::VectorType">; // Any vector where the rank is from the given `allowedRanks` list and the type // is from the given `allowedTypes` list @@ -585,10 +575,9 @@ class IsVectorOfLengthPred<list<int> allowedLengths> : // `allowedLengths` list class VectorOfLength<list<int> allowedLengths> : Type< IsVectorOfLengthPred<allowedLengths>, - " of length " # StrJoinInt<allowedLengths, "/">.result, + " of length " # !interleave(allowedLengths, "/"), "::mlir::VectorType">; - // Any vector where the number of elements is from the given // `allowedLengths` list and the type is from the given `allowedTypes` // list @@ -643,7 +632,7 @@ def F64Tensor : TensorOf<[F64]>; // Ranked tensor type with one of the specified types and ranks. class TensorRankOf<list<Type> allowedTypes, list<int> ranks> : Type<And<[TensorOf<allowedTypes>.predicate, HasAnyRankOfPred<ranks>]>, - StrJoin<!foreach(rank, ranks, rank # "D"), "/">.result # " " # + !interleave(!foreach(rank, ranks, rank # "D"), "/") # " " # TensorOf<allowedTypes>.description, "::mlir::TensorType">; class 0DTensorOf<list<Type> allowedTypes> : TensorRankOf<allowedTypes, [0]>; @@ -684,7 +673,7 @@ def F64MemRef : MemRefOf<[F64]>; // TODO: Have an easy way to add another constraint to a type. class MemRefRankOf<list<Type> allowedTypes, list<int> ranks> : Type<And<[MemRefOf<allowedTypes>.predicate, HasAnyRankOfPred<ranks>]>, - StrJoin<!foreach(rank, ranks, rank # "D"), "/">.result # " " # + !interleave(!foreach(rank, ranks, rank # "D"), "/") # " " # MemRefOf<allowedTypes>.description>; class StaticShapeMemRefOf<list<Type> allowedTypes> @@ -709,7 +698,7 @@ class AnyStridedMemRefOfRank<int rank> : class StridedMemRefRankOf<list<Type> allowedTypes, list<int> ranks> : Type<And<[MemRefOf<allowedTypes>.predicate, HasAnyRankOfPred<ranks>]>, - StrJoin<!foreach(rank, ranks, rank # "D"), "/">.result # " " # + !interleave(!foreach(rank, ranks, rank # "D"), "/") # " " # MemRefOf<allowedTypes>.description>; // This represents a generic tuple without any constraints on element type. @@ -1205,7 +1194,7 @@ class StrEnumAttr<string name, string description, StringBasedAttr< And<[StrAttr.predicate, Or<!foreach(case, cases, case.predicate)>]>, !if(!empty(description), "allowed string cases: " # - StrJoin<!foreach(case, cases, "'" # case.symbol # "'")>.result, + !interleave(!foreach(case, cases, "'" # case.symbol # "'"), ", "), description)>; // An enum attribute backed by IntegerAttr. @@ -1218,7 +1207,7 @@ class IntEnumAttr<I intType, string name, string description, EnumAttrInfo<name, cases>, SignlessIntegerAttrBase<intType, !if(!empty(description), "allowed " # intType.description # " cases: " # - StrJoinInt<!foreach(case, cases, case.value)>.result, description)> { + !interleave(!foreach(case, cases, case.value), ", "), description)> { let predicate = And<[ SignlessIntegerAttrBase<intType, "">.predicate, Or<!foreach(case, cases, case.predicate)>]>; @@ -1256,7 +1245,7 @@ class BitEnumAttr<string name, string description, I32Attr.predicate, // Make sure we don't have unknown bit set. CPred<"!($_self.cast<::mlir::IntegerAttr>().getValue().getZExtValue() & (~(" - # StrJoin<!foreach(case, cases, case.value # "u"), "|">.result # + # !interleave(!foreach(case, cases, case.value # "u"), "|") # ")))"> ]>; @@ -1347,13 +1336,13 @@ class RankedSignlessIntElementsAttr<int width, list<int> dims> : let predicate = And<[ SignlessIntElementsAttr<width>.predicate, CPred<"$_self.cast<::mlir::DenseIntElementsAttr>().getType().getShape() == " - "::mlir::ArrayRef<int64_t>({" # StrJoinInt<dims>.result # "})">]>; + "::mlir::ArrayRef<int64_t>({" # !interleave(dims, ", ") # "})">]>; let description = width # "-bit signless int elements attribute of shape [" # - StrJoinInt<dims>.result # "]"; + !interleave(dims, ", ") # "]"; let constBuilderCall = "::mlir::DenseIntElementsAttr::get(" - "::mlir::RankedTensorType::get({" # StrJoinInt<dims>.result # + "::mlir::RankedTensorType::get({" # !interleave(dims, ", ") # "}, $_builder.getIntegerType(" # width # ")), ::llvm::makeArrayRef($0))"; } @@ -1389,15 +1378,15 @@ class RankedFloatElementsAttr<int width, list<int> dims> : ElementsAttrBase< // Check that this is ranked and has the specified shape. "$_self.cast<::mlir::DenseFPElementsAttr>().getType().hasRank() && " "$_self.cast<::mlir::DenseFPElementsAttr>().getType().getShape() == " - "::mlir::ArrayRef<int64_t>({" # StrJoinInt<dims>.result # "})">, + "::mlir::ArrayRef<int64_t>({" # !interleave(dims, ", ") # "})">, width # "-bit float elements attribute of shape [" # - StrJoinInt<dims>.result # "]"> { + !interleave(dims, ", ") # "]"> { let storageType = [{ ::mlir::DenseFPElementsAttr }]; let returnType = [{ ::mlir::DenseFPElementsAttr }]; let constBuilderCall = "::mlir::DenseElementsAttr::get(" - "::mlir::RankedTensorType::get({" # StrJoinInt<dims>.result # + "::mlir::RankedTensorType::get({" # !interleave(dims, ", ") # "}, $_builder.getF" # width # "Type()), " "::llvm::makeArrayRef($0)).cast<::mlir::DenseFPElementsAttr>()"; let convertFromStorage = "$_self"; @@ -1501,7 +1490,7 @@ class StructAttr<string name, Dialect d, DictionaryAttrBase<CPred<"$_self.isa<" # d.cppNamespace # "::" # name # ">()">, "DictionaryAttr with field(s): " # - StrJoin<!foreach(a, attributes, "'" # a.name # "'"), ", ">.result # + !interleave(!foreach(a, attributes, "'" # a.name # "'"), ", ") # " (each field having its own constraints)"> { // Name for this StructAttr. string className = name; @@ -1803,7 +1792,7 @@ class HasParent<string op> : ParamNativeOpTrait<"HasParent", op>; class ParentOneOf<list<string> ops> - : ParamNativeOpTrait<"HasParent", StrJoin<ops>.result>; + : ParamNativeOpTrait<"HasParent", !interleave(ops, ", ")>; // Op result type is derived from the first attribute. If the attribute is an // subclass of `TypeAttrBase`, its value is used, otherwise, the type of the @@ -2170,7 +2159,7 @@ class ElementType<string name> : StrFunc<"getElementTypeOrSelf($" # name # ")">; class AllMatchPred<list<string> values> : CPred<"::llvm::is_splat(::llvm::makeArrayRef({" - # StrJoin<values>.result #"}))">; + # !interleave(values, ", ") #"}))">; class AllMatch<list<string> values, string description> : PredOpTrait<description, AllMatchPred<values>>; @@ -2182,7 +2171,7 @@ class AllMatchSameOperatorPred<list<string> names, string operator> : class AllMatchSameOperatorTrait<list<string> names, string operator, string description> : PredOpTrait< - "all of {" # StrJoin<names>.result # "} have same " # description, + "all of {" # !interleave(names, ", ") # "} have same " # description, AllMatchSameOperatorPred<names, operator>> { list<string> values = names; } @@ -2299,7 +2288,7 @@ class TCOpIsBroadcastableToRes<int opId, int resId> : And<[ // 2) the indices are not out of range. class TCopVTEtAreSameAt<list<int> indices> : CPred< "::llvm::is_splat(::llvm::map_range(" - "::mlir::ArrayRef<unsigned>({" # StrJoinInt<indices>.result # "}), " + "::mlir::ArrayRef<unsigned>({" # !interleave(indices, ", ") # "}), " "[this](unsigned i) { return getElementTypeOrSelf(this->getOperand(i)); " "}))">; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits