Author: Jasmine Tang
Date: 2025-08-13T00:07:58-07:00
New Revision: fe0e8f3ee1c8c4aa33221a19f0cd1dec6eb32059
URL:
https://github.com/llvm/llvm-project/commit/fe0e8f3ee1c8c4aa33221a19f0cd1dec6eb32059
DIFF:
https://github.com/llvm/llvm-project/commit/fe0e8f3ee1c8c4aa33221a19f0cd1dec6eb32059.diff
Author: Nikita Popov
Date: 2025-08-13T13:15:10+02:00
New Revision: b568a1665fbf5f21f9437af3f07673a13f8ccc90
URL:
https://github.com/llvm/llvm-project/commit/b568a1665fbf5f21f9437af3f07673a13f8ccc90
DIFF:
https://github.com/llvm/llvm-project/commit/b568a1665fbf5f21f9437af3f07673a13f8ccc90.diff
Author: Mehdi Amini
Date: 2025-08-13T21:34:23+02:00
New Revision: 5dc4aba4b2de3a6388ecf9c46ae4e5a1ff906d30
URL:
https://github.com/llvm/llvm-project/commit/5dc4aba4b2de3a6388ecf9c46ae4e5a1ff906d30
DIFF:
https://github.com/llvm/llvm-project/commit/5dc4aba4b2de3a6388ecf9c46ae4e5a1ff906d30.diff
L
Author: Mehdi Amini
Date: 2025-08-13T12:42:57-07:00
New Revision: bc613cbb6a0ab1637af76249906beb6369807105
URL:
https://github.com/llvm/llvm-project/commit/bc613cbb6a0ab1637af76249906beb6369807105
DIFF:
https://github.com/llvm/llvm-project/commit/bc613cbb6a0ab1637af76249906beb6369807105.diff
L
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/153486
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llvmbot wrote:
@efriedma-quic What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/153486
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/153486
Backport 85cd3d9
Requested by: @zygoloid
>From 7c72e1eda56b221386cdaa730cc3ec9511e071b0 Mon Sep 17 00:00:00 2001
From: Richard Smith
Date: Wed, 13 Aug 2025 12:39:25 -0700
Subject: [PATCH] Work around documente
llvmbot wrote:
@llvm/pr-subscribers-llvm-support
Author: None (llvmbot)
Changes
Backport 85cd3d9
Requested by: @zygoloid
---
Full diff: https://github.com/llvm/llvm-project/pull/153486.diff
1 Files Affected:
- (modified) llvm/lib/Support/MemoryBuffer.cpp (+8-2)
``diff
diff
https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/152161
>From dbe1c1d1ede94ec75b67b8a48cdddbf3e5b196e3 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler
Date: Tue, 5 Aug 2025 10:24:07 -0500
Subject: [PATCH 1/2] [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add
suppo
https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/153204
>From 458c685063fcc35adec954acb0f0c1b36eb09c57 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler
Date: Tue, 12 Aug 2025 09:37:37 -0500
Subject: [PATCH 1/2] [NFC] Refactor target intrinsic call lowering
Refactor int
https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/133907
>From 71352be023de35aad027ffc2eb8a353396c5726e Mon Sep 17 00:00:00 2001
From: Robert Imschweiler
Date: Tue, 1 Apr 2025 08:03:16 -0500
Subject: [PATCH 1/3] [IR] Add CallBr intrinsics support
This commit adds support
@@ -2789,20 +2789,35 @@ bool IRTranslator::translateCall(const User &U,
MachineIRBuilder &MIRBuilder) {
if (translateKnownIntrinsic(CI, ID, MIRBuilder))
return true;
+ TargetLowering::IntrinsicInfo Info;
+ // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
+ bo
https://github.com/joaosaffran created
https://github.com/llvm/llvm-project/pull/153490
In order to solve a circular dependency between `DXILABI.h` and
`BinaryFormat/DXContainer.h` we need to move `getResourceClassName` into
`DXILABI.h`
>From eb334b89ccc63e74244df707c9381924df79e914 Mon Sep 1
llvmbot wrote:
@llvm/pr-subscribers-hlsl
@llvm/pr-subscribers-backend-directx
Author: None (joaosaffran)
Changes
In order to solve a circular dependency between `DXILABI.h` and
`BinaryFormat/DXContainer.h` we need to move `getResourceClassName` into
`DXILABI.h`
---
Full diff: https://gi
@@ -16476,12 +16476,12 @@ SITargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI_,
const TargetRegisterClass *RC = nullptr;
ro-i wrote:
(done via https://github.com/llvm/llvm-project/pull/153425)
https://github.com/llvm/llvm-project/p
llvmbot wrote:
@llvm/pr-subscribers-llvm-binary-utilities
Author: None (joaosaffran)
Changes
In order to solve a circular dependency between `DXILABI.h` and
`BinaryFormat/DXContainer.h` we need to move `getResourceClassName` into
`DXILABI.h`
---
Full diff: https://github.com/llvm/llvm-p
github-actions[bot] wrote:
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Author: Nikita Popov
Date: 2025-08-13T22:34:47+02:00
New Revision: d5069f8aaefd251fdc101440b72013d9b5280f21
URL:
https://github.com/llvm/llvm-project/commit/d5069f8aaefd251fdc101440b72013d9b5280f21
DIFF:
https://github.com/llvm/llvm-project/commit/d5069f8aaefd251fdc101440b72013d9b5280f21.diff
https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/133907
>From 71352be023de35aad027ffc2eb8a353396c5726e Mon Sep 17 00:00:00 2001
From: Robert Imschweiler
Date: Tue, 1 Apr 2025 08:03:16 -0500
Subject: [PATCH 1/4] [IR] Add CallBr intrinsics support
This commit adds support
https://github.com/jdenny-ornl updated
https://github.com/llvm/llvm-project/pull/128785
>From f4135207e955f6c2e358cad54a7ef6f2f18087f8 Mon Sep 17 00:00:00 2001
From: "Joel E. Denny"
Date: Wed, 19 Mar 2025 16:19:40 -0400
Subject: [PATCH 1/9] [LoopPeel] Fix branch weights' effect on block
freque
https://github.com/efriedma-quic approved this pull request.
LGTM. Should be safe for the branch.
https://github.com/llvm/llvm-project/pull/153486
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@@ -2789,20 +2789,34 @@ bool IRTranslator::translateCall(const User &U,
MachineIRBuilder &MIRBuilder) {
if (translateKnownIntrinsic(CI, ID, MIRBuilder))
return true;
+ TargetLowering::IntrinsicInfo Info;
+ bool IsTgtMemIntrinsic = TLI->getTgtMemIntrinsic(Info, CI, *MF
https://github.com/bcardosolopes edited
https://github.com/llvm/llvm-project/pull/153387
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https://github.com/bcardosolopes approved this pull request.
LGTM after nits addressed
https://github.com/llvm/llvm-project/pull/153387
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@@ -2896,6 +2898,71 @@ mlir::LogicalResult
CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
+cir::InlineAsmOp op, OpAdaptor adaptor,
+mlir::ConversionPatternRewriter &rewri
@@ -2896,6 +2898,71 @@ mlir::LogicalResult
CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
+cir::InlineAsmOp op, OpAdaptor adaptor,
+mlir::ConversionPatternRewriter &rewri
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/153246
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@@ -0,0 +1,50 @@
+## Tests that the copied DXContainer correctly has the specified headers
+## removed.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy --remove-section=FKE1 --remove-section=FKE4 %t %t.out
+# RUN: obj2yaml %t.out | FileCheck %s
+
+--- !dxcontainer
+Header:
+ Has
https://github.com/hekota commented:
LGTM, just a few comments.
https://github.com/llvm/llvm-project/pull/153246
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@@ -0,0 +1,50 @@
+## Tests that the copied DXContainer correctly has the specified headers
+## removed.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy --remove-section=FKE1 --remove-section=FKE4 %t %t.out
+# RUN: obj2yaml %t.out | FileCheck %s
+
+--- !dxcontainer
+Header:
+ Has
@@ -0,0 +1,300 @@
+## Tests that the RTS0 (root signature) part is correctly removed from the
+## copied DXContainer.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy --remove-section=RTS0 %t %t.out
+# RUN: obj2yaml %t.out | FileCheck %s
+
+## The DXContainer described below was g
@@ -0,0 +1,57 @@
+## Tests that a separate DXContainer is created with only the specified section
+## for each --split-section specified. Also ensure that the part is removed
+## from the original object.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy %t --split-section=FKE1=%t.
https://github.com/hekota commented:
Looks good, just a few comments. :)
https://github.com/llvm/llvm-project/pull/153265
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https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/153265
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@@ -0,0 +1,57 @@
+## Tests that a separate DXContainer is created with only the specified section
+## for each --split-section specified. Also ensure that the part is removed
+## from the original object.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy %t --split-section=FKE1=%t.
@@ -0,0 +1,309 @@
+## Tests that a separate DXContainer is created for the RTS0 (root signature)
+## part, specified with --split-section. Also ensure that the part is removed
+## from the original object.
+
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objcopy %t --split-section=RTS0=%t
@@ -28,6 +52,31 @@ static Error handleArgs(const CommonConfig &Config, Object
&Obj) {
return Config.ToRemove.matches(P.Name);
};
+ if (!Config.SplitSection.empty()) {
+for (StringRef Flag : Config.SplitSection) {
+ StringRef SectionName;
+ StringRef F
@@ -28,6 +52,31 @@ static Error handleArgs(const CommonConfig &Config, Object
&Obj) {
return Config.ToRemove.matches(P.Name);
};
+ if (!Config.SplitSection.empty()) {
+for (StringRef Flag : Config.SplitSection) {
+ StringRef SectionName;
+ StringRef F
@@ -126,12 +126,11 @@ ConfigManager::getDXContainerConfig() const {
Common.GapFill != 0 || Common.PadTo != 0 ||
Common.ChangeSectionLMAValAll != 0 ||
!Common.ChangeSectionAddress.empty()) {
-return createStringError(
-llvm::errc::invalid_argument,
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/153265
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https://github.com/ldionne approved this pull request.
https://github.com/llvm/llvm-project/pull/153064
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153389
>From 377c2923243eab80d39bdb249aa5ed5c60f148cb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 5 Aug 2025 19:46:09 +0900
Subject: [PATCH] ARM: Move half convert libcall config to tablegen
---
llvm/incl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153394
>From 83b3babd3eba6ecf3122d824d8d6de7c60b02c20 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 13 Aug 2025 20:20:53 +0900
Subject: [PATCH] ARM: Move gnu half convert calling conv config into tablegen
--
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153408
>From 333abd7a754ece4bbf213ae17b43f094268b41d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 13 Aug 2025 21:05:36 +0900
Subject: [PATCH] ARM: Remove remaining half convert libcall config into
tablegen
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153394
>From 83b3babd3eba6ecf3122d824d8d6de7c60b02c20 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 13 Aug 2025 20:20:53 +0900
Subject: [PATCH] ARM: Move gnu half convert calling conv config into tablegen
--
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153389
>From 377c2923243eab80d39bdb249aa5ed5c60f148cb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 5 Aug 2025 19:46:09 +0900
Subject: [PATCH] ARM: Move half convert libcall config to tablegen
---
llvm/incl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/153408
>From 333abd7a754ece4bbf213ae17b43f094268b41d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 13 Aug 2025 21:05:36 +0900
Subject: [PATCH] ARM: Remove remaining half convert libcall config into
tablegen
https://github.com/perlfu commented:
I think the following are missing?
- [ ] - llvm.amdgcn.mfma.f32.32x32x4f16
- [ ] - llvm.amdgcn.mfma.f32.16x16x4f16
https://github.com/llvm/llvm-project/pull/153026
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https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/153387
>From 5fd1ca861731daf05ea57037602be0e015525b7b Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Wed, 13 Aug 2025 18:49:31 +0800
Subject: [PATCH 1/2] [CIR] Add InlineAsmOp lowering to LLVM
---
.../CIR/L
@@ -2896,6 +2898,71 @@ mlir::LogicalResult
CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
+cir::InlineAsmOp op, OpAdaptor adaptor,
+mlir::ConversionPatternRewriter &rewri
@@ -2896,6 +2898,71 @@ mlir::LogicalResult
CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMInlineAsmOpLowering::matchAndRewrite(
+cir::InlineAsmOp op, OpAdaptor adaptor,
+mlir::ConversionPatternRewriter &rewri
https://github.com/perlfu edited
https://github.com/llvm/llvm-project/pull/153026
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https://github.com/perlfu edited
https://github.com/llvm/llvm-project/pull/153026
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