[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100519 >From f154bdbc4048a943d23480ca00b894f0853bdf73 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:27:54 +0400 Subject: [PATCH] TTI: Check legalization cost of mul overflow ISD nodes --- llv

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100520 >From c382d2f8f2e2d0660bd3f1db5007e2a5f3cfa3cc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:31:04 +0400 Subject: [PATCH] TTI: Check legalization cost of mulfix ISD nodes --- llvm/incl

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From b448d7ddbf60e4678daf2d8ec522a82ceca7d7a3 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [llvm] AMDGPU: Correct costs of saturating add/sub intrinsics (PR #100808)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/100808?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Correct costs of saturating add/sub intrinsics (PR #100808)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/100808 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100519 >From 411c9c8f9fff386807a4ff6317dbec8a3eb1cd1a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:27:54 +0400 Subject: [PATCH] TTI: Check legalization cost of mul overflow ISD nodes --- llv

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100520 >From fc18583308ccaaf60bd234af160888a669648fef Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:31:04 +0400 Subject: [PATCH] TTI: Check legalization cost of mulfix ISD nodes --- llvm/incl

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100521 >From 19f7331a579837b2657a5d0741c6633d6f8296da Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:33:23 +0400 Subject: [PATCH] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes ---

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From 6a7346484924acdfbd630096e3dbbb4b14474028 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [llvm] AMDGPU: Enable vectorization of v2f16 copysign (PR #100799)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100799 >From ba0f8f03dc491562050a65456f7ebda23a7e4210 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 22:36:33 +0400 Subject: [PATCH] AMDGPU: Enable vectorization of v2f16 copysign --- .../AMDGPU/

[llvm-branch-commits] [llvm] AMDGPU: Handle new atomicrmw metadata for fadd case (PR #96760)

arsenm wrote: ping https://github.com/llvm/llvm-project/pull/96760 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] clang/AMDGPU: Emit atomicrmw for __builtin_amdgcn_global_atomic_fadd_{f32|f64} (PR #96872)

arsenm wrote: ping https://github.com/llvm/llvm-project/pull/96872 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f16 builtins (PR #96873)

arsenm wrote: ping https://github.com/llvm/llvm-project/pull/96873 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

arsenm wrote: ping https://github.com/llvm/llvm-project/pull/96874 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for __builtin_amdgcn_global_atomic_fadd_{f32|f64} (PR #96872)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96872 >From 2e27b153cf40498f64ef9f13b69e80804c45a6a4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Jun 2024 10:58:44 +0200 Subject: [PATCH 1/2] clang/AMDGPU: Emit atomicrmw for __builtin_amdgcn_global_ato

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From c8a9e8de2d0faf678ab8d67c85c4efd8312d5d10 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f16 builtins (PR #96873)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96873 >From 7305c0477711f7b26e4ebad3cca0afa33e1defa9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:12:59 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f1

[llvm-branch-commits] [llvm] AMDGPU: Remove global/flat atomic fadd intrinics (PR #97051)

@@ -322,4 +322,36 @@ define <2 x i16> @upgrade_amdgcn_global_atomic_fadd_v2bf16_p1(ptr addrspace(1) % ret <2 x i16> %result } +declare <2 x half> @llvm.amdgcn.flat.atomic.fadd.v2f16.p0.v2f16(ptr nocapture, <2 x half>) #0 arsenm wrote: Yes, but also no. Th

[llvm-branch-commits] [llvm] AMDGPU: Remove global/flat atomic fadd intrinics (PR #97051)

@@ -1017,29 +1015,6 @@ main_body: ret void } -define amdgpu_kernel void @global_atomic_fadd_f64_noret(ptr addrspace(1) %ptr, double %data) { arsenm wrote: Depends if they are redundant or not. Some cases already tested atomicrmw, and had the intrinsic alo

[llvm-branch-commits] [llvm] AMDGPU: Remove global/flat atomic fadd intrinics (PR #97051)

@@ -75,6 +75,11 @@ Changes to the AArch64 Backend Changes to the AMDGPU Backend - +* Removed ``llvm.amdgcn.flat.atomic.fadd`` and + ``llvm.amdgcn.global.atomic.fadd`` intrinsics. Users should use the + :ref:`atomicrmw ` instruction with `fadd` and

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for __builtin_amdgcn_global_atomic_fadd_{f32|f64} (PR #96872)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96872 >From ea17c792053e32e39a7261e3bdf1673d98e4d94a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Jun 2024 10:58:44 +0200 Subject: [PATCH 1/2] clang/AMDGPU: Emit atomicrmw for __builtin_amdgcn_global_ato

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f16 builtins (PR #96873)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96873 >From 367f6897698f22c30cb7491d90ae0251bfa57af1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:12:59 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f1

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From 2c443d8a9daeb42234e585d0d9547634409952a9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From 8ac629544dcf9fa4c35310abb89491b77e3292ba Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From 55fc7946a4480b2dd1befd579805623a56f5fd1a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From 5672042d638e13794e09d981f286fef487b05206 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [llvm] [AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (PR #101619)

@@ -1679,6 +1711,12 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeFlatStorePair( return New; } +static bool needsConstraintedOpcode(const GCNSubtarget &STM, arsenm wrote: Typo needsConstraintedOpcode https://github.com/llvm/llvm-project/pull/1

[llvm-branch-commits] [llvm] [AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (PR #101619)

@@ -1696,38 +1734,51 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI, case UNKNOWN: llvm_unreachable("Unknown instruction class"); - case S_BUFFER_LOAD_IMM: + case S_BUFFER_LOAD_IMM: { +const MachineMemOperand *MMO = *CI.I->memoperands_begin()

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From 8b91156f4d94ea9afdce9e94e5b9db9747a14a9c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From c1823018e3c143a73a296a83fc7abb8627fddf12 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From 0b40726ec88b86665b5960058f076c074094a007 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f16 builtins (PR #96873)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96873 >From e45565445c39e7ae4141513d06f0e77bf11293e1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:12:59 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from {global|flat}_atomic_fadd_v2f1

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins (PR #96874)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96874 >From 90f6b5a54ba7191be4828e3d4f7fe7897240a353 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:15:26 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw from flat_atomic_{f32|f64} builtins

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtins (PR #96875)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96875 >From e3297de0ac9cbf760ffb7d7d47e2c5ddf3cba5b0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 19:34:43 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for global/flat fadd v2bf16 builtin

[llvm-branch-commits] [clang] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64 builtins (PR #96876)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96876 >From 81d035d89b1f955b4053f313a4a3080ecdc50623 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 23:18:32 +0200 Subject: [PATCH] clang/AMDGPU: Emit atomicrmw for flat/global atomic min/max f64

[llvm-branch-commits] [llvm] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics (PR #97050)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/97050 >From 2890c8300f44bf9b77698313cc962c2f31f318a2 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 27 Jun 2024 16:32:48 +0200 Subject: [PATCH] AMDGPU: Remove flat/global atomic fadd v2bf16 intrinsics These a

[llvm-branch-commits] [llvm] IR/AMDGPU: Autoupgrade amdgpu-unsafe-fp-atomics attribute (PR #101698)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/101698 Delete the attribute and annotate any atomicrmw instructions in the function with new metadata. >From f19c1c2205115215567b7860a1a9fda2489eb114 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 18 Apr 2024

[llvm-branch-commits] [llvm] AMDGPU: Stop handling legacy amdgpu-unsafe-fp-atomics attribute (PR #101699)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/101699 This is now autoupgraded to annotate atomicrmw instructions in old bitcode. >From 1f62a17f4fb8d8b28bbf7b042a039873b04574d6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 26 Jun 2024 14:13:31 +0200 Subj

[llvm-branch-commits] [llvm] IR/AMDGPU: Autoupgrade amdgpu-unsafe-fp-atomics attribute (PR #101698)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/101698 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] IR/AMDGPU: Autoupgrade amdgpu-unsafe-fp-atomics attribute (PR #101698)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/101698?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Stop handling legacy amdgpu-unsafe-fp-atomics attribute (PR #101699)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/101699?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Stop handling legacy amdgpu-unsafe-fp-atomics attribute (PR #101699)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/101699 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (PR #101619)

@@ -1735,8 +1735,10 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI, case UNKNOWN: llvm_unreachable("Unknown instruction class"); case S_BUFFER_LOAD_IMM: { +// If XNACK is enabled, use the constrained opcodes when the first load is +// unde

[llvm-branch-commits] [llvm] AMDGPU: Support VALU add instructions in localstackalloc (PR #101692)

@@ -797,6 +797,23 @@ int64_t SIRegisterInfo::getScratchInstrOffset(const MachineInstr *MI) const { int64_t SIRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { + switch (MI->getOpcode()) {

[llvm-branch-commits] [llvm] AMDGPU: Support VALU add instructions in localstackalloc (PR #101692)

@@ -877,6 +948,86 @@ Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const { const SIInstrInfo *TII = ST.getInstrIn

[llvm-branch-commits] [llvm] release/19.x: [AMDGPU] Include `` in AMDGPUMCTargetDesc (#101766) (PR #101796)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/101796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Add a pass parameter `closed-world` for AMDGPUAttributor pass (PR #101760)

@@ -661,6 +662,24 @@ Error AMDGPUTargetMachine::buildCodeGenPipeline( return CGPB.buildPipeline(MPM, Out, DwoOut, FileType); } +Expected +parseAMDGPUAttributorPassOptions(StringRef Params) { + AMDGPUAttributorOptions Result; + while (!Params.empty()) { +StringRef Param

[llvm-branch-commits] [llvm] AMDGPU: Handle folding frame indexes into s_add_i32 (PR #101694)

@@ -0,0 +1,930 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle masked load and store intrinsics (PR #102007)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102007 None >From 0cd0fd76cf0c4bd5139f5ae138c32da5c0c154c4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 5 Aug 2024 19:49:31 +0400 Subject: [PATCH] InferAddressSpaces: Handle masked load and store intrinsics

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle masked load and store intrinsics (PR #102007)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102007?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle masked load and store intrinsics (PR #102007)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102007?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle masked load and store intrinsics (PR #102007)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102007 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (PR #101619)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/101619 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102010 None >From 2dde2add87950b6016cbb1d6c6aa979731378a1b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 5 Aug 2024 20:27:07 +0400 Subject: [PATCH] InferAddressSpaces: Handle llvm.is.constant --- .../Trans

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102010?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102010 >From 227f60ec2454ade7df9715c84f6d83840872c18d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 5 Aug 2024 20:27:07 +0400 Subject: [PATCH] InferAddressSpaces: Handle llvm.is.constant --- .../Transforms/

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

@@ -429,6 +430,15 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands( appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(0), PostorderStack, Visited); break; + case Intrinsic::is_constant: {

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

@@ -429,6 +430,15 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands( appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(0), PostorderStack, Visited); break; + case Intrinsic::is_constant: {

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

@@ -429,6 +430,15 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands( appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(0), PostorderStack, Visited); break; + case Intrinsic::is_constant: {

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle llvm.is.constant (PR #102010)

arsenm wrote: ### Merge activity * **Aug 5, 4:10 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/102010). https://github.com/llvm/llvm-project/pull/102010 _

[llvm-branch-commits] [llvm] InferAddressSpaces: Handle masked load and store intrinsics (PR #102007)

arsenm wrote: ### Merge activity * **Aug 5, 4:10 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/102007). https://github.com/llvm/llvm-project/pull/102007 _

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Fix isExtractHiElt when selecting fma_mix (PR #102130)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/102130 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [GlobalISel] Don't remove from unfinalized GISelWorkList (PR #102158)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/102158 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100519 >From fd7e3162be6e57d62942759b10e9a3e192af2d18 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:27:54 +0400 Subject: [PATCH] TTI: Check legalization cost of mul overflow ISD nodes --- llv

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100520 >From 05c9703c68a33729e598862f5b2de37e2d6a453f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:31:04 +0400 Subject: [PATCH] TTI: Check legalization cost of mulfix ISD nodes --- llvm/incl

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100521 >From 88fe51a9f4144094036da1899f5946ebfa609971 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:33:23 +0400 Subject: [PATCH] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes ---

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From bbd9d3db15809593b5d4c8d41f5990702843bf2e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Add a pass parameter `closed-world` for AMDGPUAttributor pass (PR #101760)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/101760 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [CalcSpillWeights] Avoid x87 excess precision influencing weight result (PR #102207)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/102207 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Fold frame indexes into s_or_b32 and s_and_b32 (PR #102345)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102345 Some pointer adds get turned into ors, and sometimes and is performed on pointers for masking. >From ac17eedeea4d38a7bd490ffed9b38b241e4098dc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 2 Aug 2024 1

[llvm-branch-commits] [llvm] AMDGPU: Fold frame indexes into s_or_b32 and s_and_b32 (PR #102345)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102345?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] [WIP] AMDGPU: Handle v_add* in eliminateFrameIndex (PR #102346)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102346?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Fold frame indexes into s_or_b32 and s_and_b32 (PR #102345)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102345 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [WIP] AMDGPU: Handle v_add* in eliminateFrameIndex (PR #102346)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102346 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100519 >From b6e75f2f13cc19ebf9af9b31d3c468bb9e8c225c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:27:54 +0400 Subject: [PATCH] TTI: Check legalization cost of mul overflow ISD nodes --- llv

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100520 >From 20152492bb332146d51e0b1b8175496d8101d5cb Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:31:04 +0400 Subject: [PATCH] TTI: Check legalization cost of mulfix ISD nodes --- llvm/incl

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100521 >From d428b6040084690055e06cd246cd7afa56c971b7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:33:23 +0400 Subject: [PATCH] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes ---

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From 65c4d58c92229ce1da969b1c8a63b54bf205260a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102462 None >From a8852f01f7e78e787af16e476d499025b849caea Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Aug 2024 15:48:52 +0400 Subject: [PATCH] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102462?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102462 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102470 None >From 01182f305e400b890a5829f6da78b01a2968adaa Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Aug 2024 18:02:11 +0400 Subject: [PATCH] AMDGPU: Preserve atomicrmw name when specializing address

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102470?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/102470 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102470 >From 9a8669ae34430b5e1460a948993eccc4ae917f60 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Aug 2024 18:02:11 +0400 Subject: [PATCH] AMDGPU: Preserve atomicrmw name when specializing address space

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102470 >From dd1cd7103b426389c879c0a54d23c61910f6553f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Aug 2024 18:02:11 +0400 Subject: [PATCH] AMDGPU: Preserve atomicrmw name when specializing address space

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

@@ -647,6 +647,14 @@ class LangOptions : public LangOptionsBase { return ConvergentFunctions; } + /// Return true if atomicrmw operations targeting allocations in private arsenm wrote: This has nothing to do with the target, this is language semantics.

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

@@ -550,6 +551,16 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata( CodeGenFunction &CGF, llvm::AtomicRMWInst &RMW) const { + + if (RMW.getPointerAddressSpace() == llvm::AMDGPUAS::FLAT_ADDRE

[llvm-branch-commits] [clang] clang/AMDGPU: Set noalias.addrspace metadata on atomicrmw (PR #102462)

@@ -647,6 +647,14 @@ class LangOptions : public LangOptionsBase { return ConvergentFunctions; } + /// Return true if atomicrmw operations targeting allocations in private + /// memory are undefined. + bool threadPrivateMemoryAtomicsAreUndefined() const { +// Shoul

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/102470 >From 10020575a78d050fcc927de6de942e4346af41e6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Aug 2024 18:02:11 +0400 Subject: [PATCH] AMDGPU: Preserve atomicrmw name when specializing address space

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

arsenm wrote: ### Merge activity * **Aug 8, 3:40 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/100520). https://github.com/llvm/llvm-project/pull/100520 _

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

arsenm wrote: ### Merge activity * **Aug 8, 3:40 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/100519). https://github.com/llvm/llvm-project/pull/100519 _

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From 9c21872a5ab0b5e91b90701326a672f4b73b463d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [llvm] AMDGPU: Preserve atomicrmw name when specializing address space (PR #102470)

arsenm wrote: ### Merge activity * **Aug 8, 4:33 PM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/102470). https://github.com/llvm/llvm-project/pull/102470 _

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/100523 >From ef1f347a20205255e14735e0809c2168f4124556 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 25 Jul 2024 10:38:11 +0400 Subject: [PATCH] TTI: Check legalization cost of abs nodes Also adjust the AMDGP

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

arsenm wrote: ### Merge activity * **Aug 9, 4:27 AM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/100523). https://github.com/llvm/llvm-project/pull/100523 _

[llvm-branch-commits] [llvm] AMDGPU: Correct costs of saturating add/sub intrinsics (PR #100808)

arsenm wrote: ### Merge activity * **Aug 9, 4:27 AM EDT**: @arsenm started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/100808). https://github.com/llvm/llvm-project/pull/100808 _

[llvm-branch-commits] [llvm] AMDGPU: Add noalias.addrspace metadata when autoupgrading atomic intrinsics (PR #102599)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102599 This will be needed to continue generating the raw instruction in the flat case. >From be3f530768b923491b5747bac5b005779bd46a7e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 9 Aug 2024 14:51:41 +0400

[llvm-branch-commits] [llvm] AMDGPU: Add noalias.addrspace metadata when autoupgrading atomic intrinsics (PR #102599)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/102599?utm_source=stack-comment-downstack-mergeability-warning";

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